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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

TPS65086100RSKR

Texas Instruments · Power Management - Specialized · VQFN-64-EP(8x8)

TPS65086100RSKR from Texas Instruments, in a VQFN-64-EP(8x8). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	FBGND2	power_in	Remote negative feedback sense for BUCK2 controller; connect to negative terminal of output capacitor or ground when not in use.
2	FBVOUT2	input	Remote positive feedback sense for BUCK2 controller; connect to positive terminal of output capacitor or ground when not in use.
3	DRVH2	output	High-side gate driver output for BUCK2 controller; leave floating when not in use.
4	SW2	passive	Switch node connection for BUCK2 controller; connect to ground when not in use.
5	BOOT2	passive	Bootstrap pin for BUCK2 controller; connect 100nF ceramic capacitor between this pin and SW2.
6	PGNDSNS2	power_in	Power ground sense for BUCK2; connect to ground terminal of external low-side FET or ground when not in use.
7	DRVL2	output	Low-side gate driver output for BUCK2 controller; leave floating when not in use.
8	DRV5V_2_A1	power_in	5V supply to BUCK2 gate driver and LDOA1; bypass to ground with 2.2µF ceramic capacitor.
9	LDOA1	output	LDOA1 LDO output with 200mA capability; bypass to ground with 4.7µF ceramic capacitor.
10	LX3	passive	Switch node connection for BUCK3 converter; leave floating when not in use.
11	PVIN3	power_in	Power input to BUCK3 converter (3V to 5.5V); bypass to ground with 10µF ceramic capacitor.
12	FB3	input	Remote feedback sense for BUCK3 converter with 3A output; connect to positive terminal of output capacitor or ground when not in use.
13	CTL1	input	Active-high VR enable pin; a group of VRs can be assigned to be enabled or disabled at assertion or deassertion.
14	CTL6/SLPENB2	input	Active-high VR enable pin or when configured as active-low sleep enable for VRs to enter sleep state.
15	IRQB	tri_state	Open-drain output interrupt pin; requires 7V supply for OTP programming and bypassing to ground with 1µF capacitor.
16	GPO1	output	General purpose output configurable as open-drain or push-pull to reflect Power Good status or controlled by I2C register.
17	SWB1	output	Output of load switch B1 with 300mA capability; bypass to ground with 0.1µF ceramic capacitor.
18	PVINSWB1_B2	power_in	Power supply to load switches B1 and B2; bypass to ground with 1µF ceramic capacitor for transient performance.
19	SWB2	output	Output of load switch B2 with 300mA capability; bypass to ground with 0.1µF ceramic capacitor.
20	LX5	passive	Switch node connection for BUCK5 converter; leave floating when not in use.
21	PVIN5	power_in	Power input to BUCK5 converter (3V to 5.5V); bypass to ground with 10µF ceramic capacitor.
22	FB5	input	Remote feedback sense for BUCK5 converter with 3A output; connect to positive terminal of output capacitor or ground when not in use.
23	FB4	input	Remote feedback sense for BUCK4 converter with 3A output; connect to positive terminal of output capacitor or ground when not in use.
24	PVIN4	power_in	Power input to BUCK4 converter (3V to 5.5V); bypass to ground with 10µF ceramic capacitor.
25	LX4	passive	Switch node connection for BUCK4 converter; leave floating when not in use.
26	GPO2	output	General purpose output configurable as open-drain or push-pull to reflect Power Good status or controlled by I2C register.
27	GPO3	output	General purpose output configurable as open-drain or push-pull to reflect Power Good status or controlled by I2C register.
28	GPO4	tri_state	Open-drain output configurable to reflect Power Good status or controlled by I2C register bit.
29	FBVOUT1	input	Remote feedback sense for BUCK1 controller; connect to positive terminal of output capacitor or ground when not in use.
30	ILIM1	input	Current limit set pin for BUCK1 controller; fit resistor from this pin to ground to set current limit or connect to ground when not in use.
31	SWA1	output	Output of load switch A1 with 300mA capability; bypass to ground with 0.1µF ceramic capacitor.
32	PVINSWA1	power_in	Power supply to load switch A1; bypass to ground with 1µF ceramic capacitor for transient performance.
33	DRVH1	output	High-side gate driver output for BUCK1 controller; leave floating when not in use.
34	SW1	passive	Switch node connection for BUCK1 controller; connect to ground when not in use.
35	BOOT1	passive	Bootstrap pin for BUCK1 controller; connect 100nF ceramic capacitor between this pin and SW1.
36	PGNDSNS1	power_in	Power ground sense for BUCK1; connect to ground terminal of external low-side FET or ground when not in use.
37	DRVL1	output	Low-side gate driver output for BUCK1 controller; leave floating when not in use.
38	DRV5V_1_6	power_in	5V supply to BUCK1 and BUCK6 gate drivers; bypass to ground with 2.2µF ceramic capacitor.
39	DRVL6	output	Low-side gate driver output for BUCK6 controller; leave floating when not in use.
40	PGNDSNS6	power_in	Power ground sense for BUCK6; connect to ground terminal of external low-side FET or ground when not in use.
41	BOOT6	passive	Bootstrap pin for BUCK6 controller; connect 100nF ceramic capacitor between this pin and SW6.
42	SW6	passive	Switch node connection for BUCK6 controller; connect to ground when not in use.
43	DRVH6	output	High-side gate driver output for BUCK6 controller; leave floating when not in use.
44	FBVOUT6	input	Remote feedback sense for BUCK6 controller and reference voltage for VTT LDO regulation; connect to positive terminal or ground when not in use.
45	ILIM6	input	Current limit set pin for BUCK6 controller; fit resistor from this pin to ground to set current limit or connect to ground when not in use.
46	PVINVTT	power_in	Power supply to VTT LDO; bypass to ground with minimum 10µF ceramic capacitor.
47	VTT	output	Output of VTT LDO for DDR memory termination; bypass to ground with 2× 22µF minimum ceramic capacitors.
48	VTTFB	input	Remote feedback sense for VTT LDO; connect to positive terminal of output capacitor or ground when not in use.
49	LDOA3	output	LDOA3 LDO output with 0.7V to 1.5V range and 600mA capability; bypass to ground with 4.7µF ceramic capacitor.
50	PVINLDOA2_A3	power_in	Power supply to LDOA2 and LDOA3; bypass to ground with 4.7µF ceramic capacitor.
51	LDOA2	output	LDOA2 LDO output with 0.7V to 1.5V range and 600mA capability; bypass to ground with 4.7µF ceramic capacitor.
52	AGND	power_in	Analog ground; do not connect to thermal pad ground and connect to ground of VREF capacitor.
53	VREF	power_in	Band-gap reference output; stabilize by connecting 100nF ceramic capacitor between this pin and quiet ground.
54	LDO3P3	output	Output of 3.3V ±5% internal LDO; bypass to ground with 4.7µF ceramic capacitor.
55	VSYS	power_in	System voltage detection (5.6V to 21V) and input to internal LDOs; bypass to ground with 1µF ceramic capacitor.
56	LDO5P0	output	Output of 5V ±5% internal LDO or internal switch to V5ANA; bypass to ground with 4.7µF ceramic capacitor.
57	V5ANA	power_in	Bias supply used by converters BUCK3, BUCK4, and BUCK5 for regulation; must be same supply as PVINx with optional ceramic capacitor for transient performance.
58	CLK	input	I2C serial clock input supporting standard (100kHz), fast (400kHz), and ultra-fast (1MHz) modes.
59	DATA	bidirectional	I2C serial data input/output supporting standard (100kHz), fast (400kHz), and ultra-fast (1MHz) modes.
60	CTL2	input	Active-high VR enable pin; a group of VRs can be assigned to be enabled or disabled at assertion or deassertion.
61	CTL3/SLPENB1	input	Active-high VR enable pin or when configured as active-low sleep enable for VRs to enter sleep state.
62	CTL4	input	Active-high VR enable pin; requires stable 7V supply during programming and generally not used for VR enable to avoid damage during OTP programming.
63	CTL5	input	Active-high VR enable pin; a group of VRs can be assigned to be enabled or disabled at assertion or deassertion.
64	ILIM2	input	Current limit set pin for BUCK2 controller; fit resistor from this pin to ground to set current limit or connect to ground when not in use.
65	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	VQFN-64-EP(8x8)
Category	Power Management (PMIC)
Pins	65

CAD (KiCad official)

Symbol: TPS65086100RSKR
Footprint: Package_DFN_QFN:QFN-64-1EP_8x8mm_P0.4mm_EP6.5x6.5mm
3D model: VQFN-64-EP(8x8) (KiCad packages3D, STEP)
3D model files: tps65086100rskr-etched.step / tps65086100rskr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps65086100rskr.step / tps65086100rskr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (146 pp, sha256 c1d4e6f8466c5c27, retrieved 2026-10-05, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF