component
TPS2114PW
Public Made by Adomby adom
Texas Instruments Monitors & Reset Circuits, TSSOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownTPS2114PW
Texas Instruments · Monitors & Reset Circuits · TSSOP-8
TPS2114PW from Texas Instruments, in a TSSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | STAT | output | Open-drain status output that is Hi-Z when the IN2 switch is on and pulls low when the IN1 switch is on or when OUT is Hi-Z. |
| 2 | D0 | input | TTL- and CMOS-compatible logic input with a 1-µA pullup that, together with D1, selects the operating mode and switch state per the truth table. |
| 3 | D1 | input | TTL- and CMOS-compatible logic input with a 1-µA pullup that, together with D0, selects the operating mode and switch state per the truth table. |
| 4 | ILIM | input | A resistor from ILIM to GND sets the current limit to 250/R(ILIM) for the TPS2114 (500/R(ILIM) for the TPS2115), and setting R(ILIM) to zero is not recommended because it disables current limiting. |
| 5 | GND | power_in | Ground reference for the device; all voltages in the absolute maximum ratings are specified with respect to GND. |
| 6 | IN2 | input | Secondary power switch input that can be enabled only when the IN2 supply is above its UVLO threshold and at least one supply exceeds the internal VDD UVLO; recommended input range 2.8 V to 5.5 V. |
| 7 | OUT | output | Power switch output; the TPS2114 continuous output current is rated at 0.9 A maximum. |
| 8 | IN1 | input | Primary power switch input that can be enabled only when the IN1 supply is above its UVLO threshold and at least one supply exceeds the internal VDD UVLO; recommended input range 2.8 V to 5.5 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-8 |
| Category | Power Management ICs |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Output sink current, STAT | IO | 5 | mA | 2 | |||
| Continuous output current, TPS2114 | IO | 0.9 | A | 2 | |||
| Input voltage range, IN1, IN2, D0, D1, ILIM | VI | -0.3 | 6 | V | Referenced to GND | 2 | |
| Output voltage range, OUT, STAT | VO | -0.3 | 6 | V | Referenced to GND | 2 | |
| Operating virtual junction temperature range | TJ | -40 | 125 | °C | 2 | ||
| Storage temperature range | Tstg | -65 | 150 | °C | 2 | ||
| Lead temperature soldering | 260 | °C | 1,6 mm (1/16 inch) from case for 10 seconds | 2 | |||
| ESD human body model | 2 | kV | Human body model | 3 | |||
| ESD charged device model | 500 | V | CDM | 3 | |||
| Input voltage at IN1 | VI | 1.5 | 5.5 | V | VI(IN2) ≥ 2.8 V | 3 | |
| Input voltage at IN1 | VI | 2.8 | 5.5 | V | VI(IN2) < 2.8 V | 3 | |
| Input voltage at IN2 | VI | 1.5 | 5.5 | V | VI(IN1) ≥ 2.8 V | 3 | |
| Input voltage at IN2 | VI | 2.8 | 5.5 | V | VI(IN1) < 2.8 V | 3 | |
| Input voltage at D0, D1 | VI | 0 | 5.5 | V | 3 | ||
| Current limit adjustment range, TPS2114 | IO(OUT) | 0.31 | 0.75 | A | 3 | ||
| Operating virtual junction temperature | TJ | -40 | 125 | °C | 3 | ||
| Drain-source on-state resistance (INx-OUT), TJ = 25°C | rDS(on) | 120 | 140 | mΩ | TJ = 25°C, VI(IN1) = VI(IN2) = 5.0 V, IL = 500 mA | 3 | |
| Drain-source on-state resistance (INx-OUT), TJ = 125°C | rDS(on) | 220 | mΩ | TJ = 125°C, VI(IN1) = VI(IN2) = 5.0 V, IL = 500 mA | 3 | ||
| Current limit accuracy, TPS2114 | 0.51 | 0.63 | 0.8 | A | R(ILIM) = 400 Ω | 4 | |
| Current limit accuracy, TPS2114 | 0.3 | 0.36 | 0.5 | A | R(ILIM) = 700 Ω | 4 | |
| Output rise time from an enable | tr | 0.5 | 1 | 1.5 | ms | TJ = 25°C, CL = 1 µF, IL = 500 mA, VI(IN1) = VI(IN2) = 5 V | 6 |
| Output fall time from a disable | tf | 0.35 | 0.5 | 0.7 | ms | TJ = 25°C, CL = 1 µF, IL = 500 mA, VI(IN1) = VI(IN2) = 5 V | 6 |
| Switch-over falling propagation delay (D1 logic 0 to 1) | tPHL2 | 2 | 3 | 10 | ms | TJ = 25°C, CL = 10 µF, IL = 500 mA, VI(IN1) = 1.5 V, VI(IN2) = 5 V, VI(D0) = 0 V; measured from D1 to 90% of VO(OUT) | 6 |
| Derating factor above TA = 25°C, TSSOP-8 (PW) | 3.87 | mW/°C | Above TA = 25°C | 2 | |||
| Power rating, TSSOP-8 (PW) | 386.84 | mW | TA ≤ 25°C | 2 | |||
| Power rating, TSSOP-8 (PW) | 212.76 | mW | TA = 70°C | 2 | |||
| Power rating, TSSOP-8 (PW) | 154.73 | mW | TA = 85°C | 2 |
CAD (KiCad official)
- Symbol:
TPS2114PW - Footprint:
Package_SO:TSSOP-8_4.4x3mm_P0.65mm - 3D model: TSSOP-8 (KiCad packages3D, STEP)
- 3D model files:
tps2114pw-etched.step/tps2114pw-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps2114pw.step/tps2114pw.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (25 pp, sha256
469b27c237157439, retrieved 2026-11-06, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).