MP8719GQ-Z from Monolithic Power Systems, in a QFN-16(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VIN	power_in	Supply voltage input for the internal MOSFET and regulators, operating from +4.5V to +26V and requiring an input capacitor to decouple the rail.
2	PGND	power_in	Power ground that should be connected with wide PCB traces and multiple vias.
3	3V3	power_in	External 3.3V VCC input for control and driver, with a recommended supply range of 3.15V to 3.5V and a 1µF decoupling capacitor placed close to 3V3 and AGND.
4	AGND	power_in	Analog ground to which the internal reference is referred, and to which the FB divider ground should be connected for better load regulation.
5	VTT	power_out	VTT LDO output that must be decoupled with a minimum 22µF ceramic capacitor placed as close to VTT as possible.
6	VDDQ	input	Input of the VTT LDO and VOUT sense for the buck output, which must never be left floating and should connect directly to the regulator output capacitor with a trace thicker than 100mil.
7	VTTREF	power_out	Buffered VTT reference output that tracks VDDQ/2 with 1% accuracy and requires a minimum 0.22µF ceramic decoupling capacitor placed close to the pin.
8	VTTS	input	VTT output sense input that should be connected directly to the VTT regulator output capacitor.
9	SW	output	Switch node output connected to the inductor and bootstrap capacitor, switching between VIN and PGND, which requires wide and short traces and should be kept away from sensitive traces due to noise.
10	BST	passive	Bootstrap pin where a capacitor connected between SW and BST is required to form the floating supply for the high-side switch driver.
11	OTW	output	Open-drain over-temperature warning output that is pulled low when junction temperature exceeds the 130°C warning threshold, and which can be left open if unused.
12	PG	output	Open-drain power-good output that is high when the output voltage is within the proper range.
13	FB	input	Feedback input from an external resistor divider from the output to GND that sets the output voltage, which should be placed as close to FB as possible with no vias on the FB traces.
14	MODE	input	Switching frequency and ultrasonic mode selection input that requires a 1% pull-down resistor.
15	EN2	input	Digital enable input that must be high together with EN1 for the VDDQ regulator, VTT LDO and VTTREF to turn on, and that turns all regulators off when low.
16	EN1	input	Digital enable input that must not float at any time; with EN1 = 1 and EN2 = 1 the VTT LDO and VTTREF are enabled, and it should be tied to GND if the VTT LDO is not used.
17	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Monolithic Power Systems
Package	QFN-16(3x3)
Category	Power Management (PMIC)
Pins	17

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage (VIN)	VIN			26	V		3
VSW (DC)	VSW	-1			V		3
VSW (25ns)	VSW	-3.6			V		3
IEN1, IEN2 input current	IEN1, IEN2			100	µA		3
All other pins voltage		-0.3		4.5	V		3
Continuous power dissipation QFN-16 (3mmx3mm)	PD			2.3	W	TA = +25°C	3
Junction temperature	TJ			150	°C		3
Lead temperature				260	°C		3
Storage temperature	TSTG	-65		150	°C		3
Supply voltage (VIN)	VIN	4.5		24	V		3
Supply voltage (VCC)	VCC	3.15		3.5	V		3
Output voltage (VDDQ)	VDDQ	0.6		3.3	V	Note 4: VDDQ must be ≤3.3V	3
IEN1, IEN2 input current	IEN1, IEN2			50	µA		3
Operating junction temperature (TJ)	TJ	-40		125	°C		3
Low-side valley current limit	ILIMIT	12	13	14	A		4
Reference voltage	VREF	594	600	606	mV		4
Soft-start time	TSStart	1.8	2.2	2.6	ms	EN to PG up	4
EN1 rising threshold	VEN1 TH	0.54	0.59	0.64	V		4
EN2 rising threshold	VEN2 TH	1.12	1.22	1.32	V		4
VCC UVLO threshold rising	VCCVth	2.9	3	3.1	V		5
VIN UVLO threshold rising	VINVTH	4.2		4.4	V		5
VTTREF output voltage tolerance to VDDQ	VTTREF/VDDQ	49.2	50	50.8	%	IVTTREF < 0.1mA, 1V < VDDQ < 1.5V	5
VTTREF output voltage tolerance to VDDQ	VTTREF/VDDQ	49	50	51	%	IVTTREF < 10mA, 1V < VDDQ < 1.5V	5
VTTREF current limit	ILIMIT VTTREF	13		15	mA		5
VTT tolerance to VTTREF	VTT-VTTREF	-15		15	mV	-10mA < IVTT < 10mA, VDDQ = [1V - 1.5V]	5
VTT tolerance to VTTREF	VTT-VTTREF	-20		20	mV	-0.6A < IVTT < 0.6A, VDDQ = [1V - 1.5V]	5
VTT tolerance to VTTREF	VTT-VTTREF	-25		25	mV	-1A < IVTT < 1A, VDDQ = [1V - 1.5V]	5
Source current limit	ILIMIT SOURCE	1.2		1.5	A		5
Sink current limit	ILIMIT SINK	1.2		1.5	A		5
Constant on timer	TON	1100	1200	1300	ns	VIN = 6V, VOUT = 3V, RMODE = 150kΩ	4
OVP threshold	VOVP	125	130	135	%VREF		4
UVP-1 threshold	VUVP-1	70	75	80	%VREF		4
UVP-2 threshold	VUVP-2	45	50	55	%VREF		4
Feedback current	IFB	10		50	nA	VFB = 0.62V	4
Switch leakage	SWLKG	0		1	μA	VEN = 0V, VSW = 0V	4
PG rising (good) threshold	PG Rising(GOOD)		95		%	VFB rising, percentage of VFB	5
PG falling (fault) threshold	PG Falling(Fault)		90		%	VFB falling, percentage of VFB	5
PG rising (fault) threshold	PG Rising(Fault)		115		%	VFB rising, percentage of VFB	5
PG falling (good) threshold	PG Falling(GOOD)		105		%	VFB falling, percentage of VFB	5
PG low to high delay	PGTd		3		μs		5
EN low to PG low delay	PGTd		1		μs	EN low	5
PG sink current capability	VPG Sink		0.4		V	4mA	5
VCC UVLO threshold hysteresis	VCCHYS		220		mV		5
VIN UVLO threshold hysteresis	VINHYS		360		mV		5
Over-temperature warning	TOTW		130		°C		5
OTW hysteresis	TOTW HYS		25		°C		5
High-side switch on resistance	HSRDS-ON		19.5		mΩ	TJ = 25°C	4
Low-side switch on resistance	LSRDS-ON		6.6		mΩ	TJ = 25°C	4
Switching frequency	FS		700		kHz	RMODE = 0Ω	4
Switching frequency	FS		500		kHz	RMODE = 150kΩ	4
Minimum on time	TON MIN		70		ns		4
Minimum off time	TOFF MIN		300		ns		4
Thermal shutdown	TSD		145		°C		5
3V3 supply current in normal mode	I3V3		185		µA	VEN1 = VEN2 = 3V, no load	4
3V3 supply current in S3 mode	I3V3_S3		135		µA	VEN1 = 0V, VEN2 = 3V, no load	4
3V3 shutdown current	I3V3 SDN		1		µA	VEN1 = VEN2 = 0V, no load	4
Junction-to-ambient thermal resistance	θJA		55		°C/W	Measured on JESD51-7, 4-layer PCB	3
Junction-to-case thermal resistance	θJC		13		°C/W		3
Enable input current	IEN1/2		5		µA	VEN1/2 = 2V	4

CAD (KiCad official)

Symbol: MP8719GQ-Z
Footprint: Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm
3D model: QFN-16(3x3) (KiCad packages3D, STEP)
3D model files: mp8719gq-z-etched.step / mp8719gq-z-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mp8719gq-z.step / mp8719gq-z.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Monolithic Power Systems datasheet (22 pp, sha256 fe5b829df6f2136e, retrieved 2026-10-31, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

MP8719GQ-Z

Verified MP8719GQ-Z

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3D Model

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Schematic Symbol

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Datasheet

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