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GD32F103RBT6

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GigaDevice Semicon Beijing Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

Schematic Symbol

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Datasheet

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Contents

README

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GD32F103RBT6

GigaDevice Semicon Beijing · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)

GD32F103RBT6 from GigaDevice Semicon Beijing, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VBAT power_in Backup-domain supply pin (default function VBAT, Table 2-7).
2 PC13-TAMPER-RTC bidirectional GPIO PC13 by default; alternate function TAMPER-RTC.
3 PC14-OSC32IN bidirectional GPIO PC14 by default; alternate function OSC32IN (low-speed oscillator input).
4 PC15-OSC32OUT bidirectional GPIO PC15 by default; alternate function OSC32OUT (low-speed oscillator output).
5 OSCIN input High-speed external (HXTAL, 4-16 MHz) oscillator input.
6 OSCOUT output High-speed external (HXTAL) oscillator output.
7 NRST bidirectional Reset pin (default function NRST).
8 PC0 bidirectional GPIO PC0 by default; alternate ADC012_IN10 (ADC channel 10).
9 PC1 bidirectional GPIO PC1 by default; alternate ADC012_IN11 (ADC channel 11).
10 PC2 bidirectional GPIO PC2 by default; alternate ADC012_IN12 (ADC channel 12).
11 PC3 bidirectional GPIO PC3 by default; alternate ADC012_IN13 (ADC channel 13).
12 VSSA power_in Analog ground for the ADC, DAC and analog blocks.
13 VDDA power_in Analog supply for the ADC, DAC and analog blocks.
14 PA0-WKUP bidirectional GPIO PA0 by default; alternate WKUP (wakeup), USART1_CTS, ADC012_IN0, TIMER1_CH0, TIMER1_ETI, TIMER4_CH0 and TIMER7_ETI.
15 PA1 bidirectional GPIO PA1 by default; alternate USART1_RTS, ADC012_IN1, TIMER1_CH1 and TIMER4_CH1.
16 PA2 bidirectional GPIO PA2 by default; alternate USART1_TX, ADC012_IN2, TIMER1_CH2, TIMER4_CH2 and TIMER8_CH0.
17 PA3 bidirectional GPIO PA3 by default; alternate USART1_RX, ADC012_IN3, TIMER1_CH3, TIMER4_CH3 and TIMER8_CH1.
18 VSS_4 power_in Digital ground.
19 VDD_4 power_in Digital supply.
20 PA4 bidirectional GPIO PA4 by default; alternate SPI0_NSS, USART1_CK, ADC01_IN4 and DAC0_OUT0; remap SPI2_NSS and I2S2_WS.
21 PA5 bidirectional GPIO PA5 by default; alternate SPI0_SCK, ADC01_IN5 and DAC0_OUT1.
22 PA6 bidirectional GPIO PA6 by default; alternate SPI0_MISO, ADC01_IN6, TIMER2_CH0, TIMER7_BRKIN and TIMER12_CH0; remap TIMER0_BRKIN.
23 PA7 bidirectional GPIO PA7 by default; alternate SPI0_MOSI, ADC01_IN7, TIMER2_CH1, TIMER7_CH0_ON and TIMER13_CH0; remap TIMER0_CH0_ON.
24 PC4 bidirectional GPIO PC4 by default; alternate ADC01_IN14.
25 PC5 bidirectional GPIO PC5 by default; alternate ADC01_IN15.
26 PB0 bidirectional GPIO PB0 by default; alternate ADC01_IN8, TIMER2_CH2 and TIMER7_CH1_ON; remap TIMER0_CH1_ON.
27 PB1 bidirectional GPIO PB1 by default; alternate ADC01_IN9, TIMER2_CH3 and TIMER7_CH2_ON; remap TIMER0_CH2_ON.
28 PB2 bidirectional 5 V tolerant GPIO PB2 by default, also used as BOOT1 per Table 2-7.
29 PB10 bidirectional 5 V tolerant GPIO PB10 by default; alternate I2C1_SCL and USART2_TX; remap TIMER1_CH2.
30 PB11 bidirectional 5 V tolerant GPIO PB11 by default; alternate I2C1_SDA and USART2_RX; remap TIMER1_CH3.
31 VSS_1 power_in Digital ground.
32 VDD_1 power_in Digital supply.
33 PB12 bidirectional 5 V tolerant GPIO PB12 by default; alternate SPI1_NSS, I2C1_SMBA, USART2_CK, TIMER0_BRKIN and I2S1_WS.
34 PB13 bidirectional 5 V tolerant GPIO PB13 by default; alternate SPI1_SCK, USART2_CTS, TIMER0_CH0_ON and I2S1_CK.
35 PB14 bidirectional 5 V tolerant GPIO PB14 by default; alternate SPI1_MISO, USART2_RTS, TIMER0_CH1_ON and TIMER11_CH0.
36 PB15 bidirectional 5 V tolerant GPIO PB15 by default; alternate SPI1_MOSI, TIMER0_CH2_ON, I2S1_SD and TIMER11_CH1.
37 PC6 bidirectional 5 V tolerant GPIO PC6 by default; alternate I2S1_MCK, TIMER7_CH0 and SDIO_D6; remap TIMER2_CH0.
38 PC7 bidirectional 5 V tolerant GPIO PC7 by default; alternate I2S2_MCK, TIMER7_CH1 and SDIO_D7; remap TIMER2_CH1.
39 PC8 bidirectional 5 V tolerant GPIO PC8 by default; alternate TIMER7_CH2 and SDIO_D0; remap TIMER2_CH2.
40 PC9 bidirectional 5 V tolerant GPIO PC9 by default; alternate TIMER7_CH3 and SDIO_D1; remap TIMER2_CH3.
41 PA8 bidirectional 5 V tolerant GPIO PA8 by default; alternate USART0_CK, TIMER0_CH0 and CK_OUT0.
42 PA9 bidirectional 5 V tolerant GPIO PA9 by default; alternate USART0_TX and TIMER0_CH1.
43 PA10 bidirectional 5 V tolerant GPIO PA10 by default; alternate USART0_RX and TIMER0_CH2.
44 PA11 bidirectional 5 V tolerant GPIO PA11 by default; alternate USART0_CTS, CAN0_RX, USBDM and TIMER0_CH3.
45 PA12 bidirectional 5 V tolerant GPIO PA12 by default; alternate USART0_RTS, CAN0_TX, TIMER0_ETI and USBDP.
46 PA13 bidirectional 5 V tolerant pin; default function JTMS/SWDIO, remap PA13.
47 VSS_2 power_in Digital ground.
48 VDD_2 power_in Digital supply.
49 PA14 bidirectional 5 V tolerant pin; default function JTCK/SWCLK, remap PA14.
50 PA15 bidirectional 5 V tolerant pin; default function JTDI, remap TIMER1_CH0, TIMER1_ETI, PA15 and SPI0_NSS; alternate SPI2_NSS and I2S2_WS.
51 PC10 bidirectional 5 V tolerant GPIO PC10 by default; alternate UART3_TX and SDIO_D2; remap USART2_TX, SPI2_SCK and I2S2_CK.
52 PC11 bidirectional 5 V tolerant GPIO PC11 by default; alternate UART3_RX and SDIO_D3; remap USART2_RX and SPI2_MISO.
53 PC12 bidirectional 5 V tolerant GPIO PC12 by default; alternate UART4_TX and SDIO_CK; remap USART2_CK, SPI2_MOSI and I2S2_SD.
54 PD2 bidirectional 5 V tolerant GPIO PD2 by default; alternate TIMER2_ETI, SDIO_CMD and UART4_RX.
55 PB3 bidirectional 5 V tolerant pin; default function JTDO; alternate SPI2_SCK and I2S2_CK; remap PB3, TRACESWO, TIMER1_CH1 and SPI0_SCK.
56 PB4 bidirectional 5 V tolerant pin; default function NJTRST; alternate SPI2_MISO; remap TIMER2_CH0, PB4 and SPI0_MISO.
57 PB5 bidirectional GPIO PB5 by default; alternate I2C0_SMBA, SPI2_MOSI and I2S2_SD; remap TIMER2_CH1 and SPI0_MOSI.
58 PB6 bidirectional 5 V tolerant GPIO PB6 by default; alternate I2C0_SCL and TIMER3_CH0; remap USART0_TX.
59 PB7 bidirectional 5 V tolerant GPIO PB7 by default; alternate I2C0_SDA and TIMER3_CH1; remap USART0_RX.
60 BOOT0 input Boot mode select input (default function BOOT0).
61 PB8 bidirectional 5 V tolerant GPIO PB8 by default; alternate TIMER3_CH2 and TIMER9_CH0; remap I2C0_SCL and CAN0_RX; SDIO_D4 is also listed.
62 PB9 bidirectional 5 V tolerant GPIO PB9 by default; alternate TIMER3_CH3 and TIMER10_CH0; remap I2C0_SDA and CAN0_TX; SDIO_D5 is also listed.
63 VSS_3 power_in Digital ground.
64 VDD_3 power_in Digital supply.

Key specifications

Parameter Value
Manufacturer GigaDevice Semicon Beijing
Package LQFP-64(10x10)
Category Embedded Processors & Controllers
Pins 64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
External voltage range VDD (relative to VSS) VDD -0.3 3.6 V Printed as VSS - 0.3 to VSS + 3.6 59
External analog supply voltage VDDA (relative to VSSA) VDDA -0.3 3.6 V Printed as VSSA - 0.3 to VSSA + 3.6 59
External battery supply voltage (relative to VSS) VBAT -0.3 3.6 V Printed as VSS - 0.3 to VSS + 3.6 59
Input voltage on 5V tolerant pin VIN -0.3 V Max printed as VDD + 3.6; VIN maximum value cannot exceed 5.5 V 59
Input voltage on other I/O (relative to VSS) VIN -0.3 3.6 V 59
Variation between different VDD power pins /ΔVDDX/ 50 mV 59
Variation between different ground pins /VSSX - VSS/ 50 mV 59
Maximum current for GPIO pins IIO -25 25 mA 59
Operating temperature range TA -40 85 °C 59
Power dissipation of LQFP64 PD 647 mW Power dissipation at TA = 85 °C of LQFP64 59
Storage temperature range TSTG -65 150 °C 59
Maximum junction temperature TJ 125 °C 59
Supply voltage VDD VDD 2.6 3.3 3.6 V 59
Analog supply voltage VDDA VDDA 2.6 3.3 3.6 V Same as VDD 59
Battery supply voltage VBAT 1.8 3.6 V 59
AHB clock frequency fHCLK 108 MHz 59
APB1 clock frequency fAPB1 54 MHz 59
APB2 clock frequency fAPB2 108 MHz 59
VDD rise time rate tVDD 0 μs/V 59
VDD fall time rate 20 μs/V 59
LVD hysteresis VLVDhyst 100 mV 69
Electrostatic discharge voltage (human body model) VESD(HBM) 3000 V TA = 25 °C; JS-001-2014 70
Electrostatic discharge voltage (charge device model) VESD(CDM) 500 V TA = 25 °C; JS-002-2014 70
Static latch-up I-test LU I-test -100 100 mA TA = 25 °C; JESD78 71
Static latch-up supply overvoltage 5.4 V 71
Crystal or ceramic frequency (HXTAL) fHXTAL 4 8 16 MHz 2.6 V ≤ VDD ≤ 3.6 V 71
Recommended matching capacitance on OSCIN and OSCOUT CHXTAL 20 30 pF 71
Crystal or ceramic duty cycle (HXTAL) Ducy(HXTAL) 30 50 70 % 71
External clock source or oscillator frequency (HXTAL bypass) fHXTAL_ext 1 50 MHz 2.6 V ≤ VDD ≤ 3.6 V 72
OSCIN rise or fall time (HXTAL bypass) tR/F(HXTAL) 10 ns 72
Duty cycle (HXTAL bypass) Ducy(HXTAL) 40 60 % 72
Crystal or ceramic duty cycle (LXTAL) Ducy(LXTAL) 30 70 % 72
External clock source or oscillator frequency (LXTAL bypass) fLXTAL_ext 32.768 1000 kHz VDD = 3.3 V 73
OSC32IN rise or fall time (LXTAL bypass) tR/F(LXTAL) 50 ns 73
Duty cycle (LXTAL bypass) Ducy(LXTAL) 30 50 70 % 73
IRC8M oscillator frequency accuracy, factory-trimmed ACCIRC8M -2.5 2.5 % VDD = VDDA = 3.3 V, TA = -40 °C ~ +85 °C 74
IRC8M oscillator frequency accuracy, factory-trimmed ACCIRC8M -1 1 % VDD = VDDA = 3.3 V, TA = 25 °C 74
IRC8M oscillator duty cycle DucyIRC8M 45 50 55 % VDD = VDDA = 3.3 V 74
PLL input clock frequency fPLLIN 1 25 MHz 75
PLL output clock frequency fPLLOUT 16 108 MHz 75
PLL VCO output clock frequency fVCO 32 216 MHz 75
PLL lock time tLOCK 300 μs 75
Number of guaranteed program/erase cycles before failure (endurance) PECYC 100 kcycles TA = -40 °C ~ +85 °C 76
Word programming time tPROG 37.5 105 μs TA = -40 °C ~ +85 °C 76
Page erase time tERASE 50 400 ms TA = -40 °C ~ +85 °C 76
Mass erase time (128K) tMERASE(128K) 2.4 24 s TA = -40 °C ~ +85 °C 76
PC13-PC15 GPIO speed in output mode (note 3) 2 MHz Output mode, maximum load 30 pF 79
ADC operating voltage VDDA VDDA 2.6 3.3 3.6 V 81
ADC clock fADC 0.6 14 MHz 81
External input impedance RAIN 54.8 kΩ See Equation 1 81
Sampling time ts 0.11 17.11 μs fADC = 14 MHz 81
USART SCK clock frequency fSCK 13.5 MHz fPCLKx = 108 MHz 89
USART SCK clock high time tSCK(H) 37 ns fPCLKx = 108 MHz 89
USART SCK clock low time tSCK(L) 37 ns fPCLKx = 108 MHz 89
SPI SCK clock frequency fSCK 27 MHz 85
SPI SCK clock high time tSCK(H) 35.13 37.13 39.13 ns Master mode, fPCLKx = 108 MHz, presc = 4 85
SPI SCK clock low time tSCK(L) 35.13 37.13 39.13 ns Master mode, fPCLKx = 108 MHz, presc = 4 85
USBD operating voltage VDD 3 3.6 V 90
Static output level low VOL 0.064 0.3 V RL of 1.5 kΩ to 3.6 V 90
Static output level high VOH 2.8 3.3 3.6 V RL of 15 kΩ to VSS 90

CAD (KiCad official)

  • Symbol: GD32F103RBT6
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: gd32f103rbt6-etched.step / gd32f103rbt6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); gd32f103rbt6.step / gd32f103rbt6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: GigaDevice Semicon Beijing datasheet (112 pp, sha256 53da1a17a1523e83, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF