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AiP74HC165TA16.TR
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Wuxi I core Elec Shift Registers, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README
markdownAiP74HC165TA16.TR
Wuxi I core Elec · Shift Registers · TSSOP-16
AiP74HC165TA16.TR from Wuxi I core Elec, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PL | input | Asynchronous parallel load input, active low; when low, D0 to D7 are loaded asynchronously into the shift register. |
| 2 | CP | input | Clock input, triggered on the low-to-high edge; data shifts on the CP rising edge when CE is low. |
| 3 | D4 | input | Parallel data input (also called Dn), loaded into the register when PL is low. |
| 4 | D5 | input | Parallel data input (also called Dn), loaded into the register when PL is low. |
| 5 | D6 | input | Parallel data input (also called Dn), loaded into the register when PL is low. |
| 6 | D7 | input | Parallel data input (also called Dn), loaded into the register when PL is low. |
| 7 | Q7-bar | output | Final-stage complementary serial output (inverse of Q7). |
| 8 | GND | power_in | Ground (0 V). |
| 9 | Q7 | output | Final-stage serial output. |
| 10 | DS | input | Serial data input, clocked into the register on the CP rising edge while PL is high. |
| 11 | D0 | input | Parallel data input (also called Dn), loaded into the register when PL is low. |
| 12 | D1 | input | Parallel data input (also called Dn), loaded into the register when PL is low. |
| 13 | D2 | input | Parallel data input (also called Dn), loaded into the register when PL is low. |
| 14 | D3 | input | Parallel data input (also called Dn), loaded into the register when PL is low. |
| 15 | CE | input | Clock enable input, active low; a high level on CE disables the CP input. |
| 16 | VCC | power_in | Supply voltage; the AiP74HC165 recommended range is 2.0 V to 6.0 V, with an absolute maximum of +7 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Wuxi I core Elec |
| Package | TSSOP-16 |
| Category | Logic |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | -0.5 | 7 | V | 8 | ||
| Input clamp current | IIK | -20 | 20 | mA | VI<-0.5V 或 VI>VCC+0.5V | 8 | |
| Output clamp current | IOK | -20 | 20 | mA | VO<-0.5V 或 VO>VCC+0.5V | 8 | |
| Output current | IO | -25 | 25 | mA | -0.5V<VO<VCC+0.5V | 8 | |
| Supply current | ICC | 50 | mA | 8 | |||
| Ground current | IGND | -50 | mA | 8 | |||
| Total power dissipation | Ptot | 500 | mW | 8 | |||
| Storage temperature | Tstg | -65 | 150 | ℃ | 8 | ||
| Supply voltage (recommended, AiP74HC165) | VCC | 2 | 5 | 6 | V | 8 | |
| Input voltage | VI | 0 | V | 8 | |||
| Output voltage | VO | 0 | V | 8 | |||
| Input rise and fall rate | Δt/ΔV | 625 | ns/V | VCC=2.0V | 8 | ||
| Input rise and fall rate | Δt/ΔV | 1.67 | 139 | ns/V | VCC=4.5V | 8 | |
| Input rise and fall rate | Δt/ΔV | 83 | ns/V | VCC=6.0V | 8 | ||
| Operating ambient temperature | Tamb | -40 | 105 | ℃ | 8 | ||
| High-level input voltage | VIH | 1.5 | V | VCC=2.0V | 11 | ||
| High-level input voltage | VIH | 3.15 | V | VCC=4.5V | 11 | ||
| High-level input voltage | VIH | 4.2 | V | VCC=6.0V | 11 | ||
| Low-level input voltage | VIL | 0.5 | V | VCC=2.0V | 11 | ||
| Low-level input voltage | VIL | 1.35 | V | VCC=4.5V | 11 | ||
| Low-level input voltage | VIL | 1.8 | V | VCC=6.0V | 11 | ||
| High-level output voltage | VOH | 1.9 | V | VI=VIH或VIL；IO=-20uA；VCC=2.0V | 11 | ||
| High-level output voltage | VOH | 4.4 | V | VI=VIH或VIL；IO=-20uA；VCC=4.5V | 11 | ||
| High-level output voltage | VOH | 5.9 | V | VI=VIH或VIL；IO=-20uA；VCC=6.0V | 11 | ||
| High-level output voltage | VOH | 3.7 | V | VI=VIH或VIL；IO=-4.0mA；VCC=4.5V | 11 | ||
| High-level output voltage | VOH | 5.2 | V | VI=VIH或VIL；IO=-5.2mA；VCC=6.0V | 11 | ||
| Low-level output voltage | VOL | 0.1 | V | VI=VIH或VIL；IO=20uA；VCC=2.0V | 11 | ||
| Low-level output voltage | VOL | 0.4 | V | VI=VIH或VIL；IO=4.0mA；VCC=4.5V | 11 | ||
| Input leakage current | II | -1 | 1 | uA | VI=VCC或GND；VCC=6.0V | 11 | |
| Quiescent supply current | ICC | 160 | uA | VI=VCC或GND；IO=0A；VCC=6.0V | 11 | ||
| Propagation delay CP,CE to Q7,Q7 bar | tpd | 250 | ns | CP,CE到Q7,Q7̄；见图6；VCC=2.0V | 16 | ||
| Propagation delay CP,CE to Q7,Q7 bar | tpd | 50 | ns | CP,CE到Q7,Q7̄；见图6；VCC=4.5V | 16 | ||
| Propagation delay CP,CE to Q7,Q7 bar | tpd | 43 | ns | CP,CE到Q7,Q7̄；见图6；VCC=6.0V | 16 | ||
| Propagation delay PL to Q7,Q7 bar | tpd | 250 | ns | PL到Q7,Q7̄；见图7；VCC=2.0V | 16 | ||
| Propagation delay PL to Q7,Q7 bar | tpd | 50 | ns | PL到Q7,Q7̄；见图7；VCC=4.5V | 16 | ||
| Propagation delay PL to Q7,Q7 bar | tpd | 43 | ns | PL到Q7,Q7̄；见图7；VCC=6.0V | 16 | ||
| Propagation delay D7 to Q7,Q7 bar | tpd | 180 | ns | D7到Q7,Q7̄；见图8；VCC=2.0V | 16 | ||
| Propagation delay D7 to Q7,Q7 bar | tpd | 36 | ns | D7到Q7,Q7̄；见图8；VCC=4.5V | 16 | ||
| Propagation delay D7 to Q7,Q7 bar | tpd | 31 | ns | D7到Q7,Q7̄；见图8；VCC=6.0V | 16 | ||
| Transition time Q7,Q7 bar output | tt | 110 | ns | Q7,Q7̄输出；见图6；VCC=2.0V | 16 | ||
| Transition time Q7,Q7 bar output | tt | 22 | ns | Q7,Q7̄输出；见图6；VCC=4.5V | 16 | ||
| Transition time Q7,Q7 bar output | tt | 19 | ns | Q7,Q7̄输出；见图6；VCC=6.0V | 16 | ||
| Pulse width CP input high or low | tW | 120 | ns | CP输入高电平或低电平；见图6；VCC=2.0V | 16 | ||
| Pulse width CP input high or low | tW | 24 | ns | CP输入高电平或低电平；见图6；VCC=4.5V | 16 | ||
| Pulse width CP input high or low | tW | 20 | ns | CP输入高电平或低电平；见图6；VCC=6.0V | 16 | ||
| Recovery time PL to CP,CE | trec | 150 | ns | PL到CP,CE；见图7；VCC=2.0V | 16 | ||
| Recovery time PL to CP,CE | trec | 30 | ns | PL到CP,CE；见图7；VCC=4.5V | 16 | ||
| Recovery time PL to CP,CE | trec | 26 | ns | PL到CP,CE；见图7；VCC=6.0V | 16 | ||
| Setup time DS to CP,CE | tsu | 120 | ns | DS到CP,CE；见图9；VCC=2.0V | 16 | ||
| Setup time DS to CP,CE | tsu | 24 | ns | DS到CP,CE；见图9；VCC=4.5V | 16 | ||
| Setup time DS to CP,CE | tsu | 20 | ns | DS到CP,CE；见图9；VCC=6.0V | 16 | ||
| Hold time DS to CP,CE and Dn to PL | th | 5 | ns | DS到CP,CE和Dn到PL；见图9；VCC=2.0V | 16 | ||
| Maximum clock frequency | fmax | 5 | MHz | CP输入；见图6；VCC=2.0V | 16 | ||
| Maximum clock frequency | fmax | 20 | MHz | CP输入；见图6；VCC=4.5V | 16 | ||
| Maximum clock frequency | fmax | 24 | MHz | CP输入；见图6；VCC=6.0V | 16 |
CAD (KiCad official)
- Symbol:
AiP74HC165TA16.TR - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
aip74hc165ta16-tr-etched.step/aip74hc165ta16-tr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);aip74hc165ta16-tr.step/aip74hc165ta16-tr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Wuxi I core Elec datasheet (25 pp, sha256
12b24493bdbea83f, retrieved 2026-10-20, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).