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TSV521AICT

Public Made by Adom

by adom

STMicroelectronics Operational Amplifier, SC-70-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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TSV521AICT

STMicroelectronics · Operational Amplifier · SC-70-5

TSV521AICT from STMicroelectronics, in a SC-70-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN+ input Non-inverting input; the input common-mode range extends from VCC- - 0.1 V to VCC+ + 0.1 V, and the input current must not exceed 10 mA (limit it with a series resistor if needed).
2 VCC- power_in Negative supply rail, 0 V in the datasheet test conditions; the input common-mode range extends to 0.1 V below this pin.
3 IN- input Inverting input; the input common-mode range extends from VCC- - 0.1 V to VCC+ + 0.1 V, and the input current must not exceed 10 mA (limit it with a series resistor if needed).
4 OUT output Amplifier output, which swings to within 35 mV maximum of each rail when loaded with 10 kΩ to VCC/2.
5 VCC+ power_in Positive supply rail, specified from 2.7 V to 5.5 V; place a 10 nF decoupling capacitor as close as possible to this pin.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package SC-70-5
Category Amplifiers/Comparators
Pins 5

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 2.7 5.5 V 4
Operating free air temperature range Toper -40 125 °C 4
Supply voltage VCC 6 V 4
Input current Iin 10 mA 4
Storage temperature Tstg -65 150 °C 4
Maximum junction temperature Tj 150 °C 4
ESD HBM: human body model ESD 4 kV Human body model 4
ESD MM: machine model ESD 300 V Machine model 4
ESD CDM: charged device model (SC70-5 and DFN8) ESD 1.3 kV SC70-5 and DFN8 packages 4
Input offset voltage (TSV52xA) Vio 600 µV VCC+ = 5 V, T = 25 °C 7
Input offset voltage (TSV52xA) Vio 2400 µV VCC+ = 5 V, -40 °C < T < 125 °C 7
Input offset voltage drift ΔVio/ΔT 3 18 µV/°C -40 °C < T < 125 °C 7
Input offset current Iio 1 10 pA Vout = VCC/2, T = 25 °C 7
Input offset current Iio 1 100 pA Vout = VCC/2, -40 °C < T < 125 °C 7
Input bias current Iib 1 10 pA Vout = VCC/2, T = 25 °C 7
Input bias current Iib 1 100 pA Vout = VCC/2, -40 °C < T < 125 °C 7
Common-mode rejection ratio (CMR1) CMR1 54 76 dB Vic = -0.1 V to VCC +0.1 V, Vout = VCC/2, RL = 1 MΩ, T = 25 °C 7
Common-mode rejection ratio (CMR1) CMR1 50 dB Vic = -0.1 V to VCC +0.1 V, Vout = VCC/2, RL = 1 MΩ, -40 °C < T < 125 °C 7
Common-mode rejection ratio (CMR2) CMR2 63 84 dB Vic = 1 V to VCC -1 V, Vout = VCC/2, RL = 1 MΩ, T = 25 °C 7
Common-mode rejection ratio (CMR2) CMR2 58 dB Vic = 1 V to VCC -1 V, Vout = VCC/2, RL = 1 MΩ, -40 °C < T < 125 °C 7
Supply voltage rejection ratio SVR 65 87 dB VCC = 2.7 V to 5.5 V, Vout = VCC/2, T = 25 °C 8
Supply voltage rejection ratio SVR 60 dB VCC = 2.7 V to 5.5 V, Vout = VCC/2, -40 °C < T < 125 °C 8
Large signal voltage gain Avd 94 109 Vout = 0.5 V to (VCC - 0.5 V), RL = 1 MΩ, T = 25 °C 8
Large signal voltage gain Avd 68 Vout = 0.5 V to (VCC - 0.5 V), RL = 1 MΩ, -40 °C < T < 125 °C 8
High level output voltage VOH 5 35 mV T = 25 °C 8
High level output voltage VOH 50 mV -40 °C < T < 125 °C 8
Low level output voltage VOL 9 35 mV T = 25 °C 8
Low level output voltage VOL 50 mV -40 °C < T < 125 °C 8
Output sink current Isink 36 55 mA Vout = VCC, T = 25 °C 8
Output sink current Isink 27 mA Vout = VCC, -40 °C < T < 125 °C 8
Output source current Isource 36 55 mA Vout = 0 V, T = 25 °C 8
Output source current Isource 27 mA Vout = 0 V, -40 °C < T < 125 °C 8
Supply current (per channel) ICC 45 60 µA Vout = VCC/2, RL > 1 MΩ, T = 25 °C 8
Gain bandwidth product GBP 0.73 1.15 MHz RL = 10 kΩ, CL = 100 pF 8
Input offset voltage (TSV52xA) Vio 800 µV VCC+ = 2.7 V, T = 25 °C 5
Input offset voltage (TSV52xA) Vio 2600 µV VCC+ = 2.7 V, -40 °C < T < 125 °C 5
Input offset current Iio 1 10 pA VCC+ = 2.7 V, Vout = VCC/2, T = 25 °C 5
Input bias current Iib 1 10 pA VCC+ = 2.7 V, Vout = VCC/2, T = 25 °C 5
Common-mode rejection ratio CMR 50 72 dB VCC+ = 2.7 V, Vic = -0.1 V to VCC+0.1V, Vout = VCC/2, RL = 1 MΩ, T = 25 °C 5
Large signal voltage gain Avd 90 105 VCC+ = 2.7 V, Vout = 0.5 V to (VCC - 0.5V), RL = 1 MΩ, T = 25 °C 5
High level output voltage VOH 3 35 mV VCC+ = 2.7 V, T = 25 °C 5
Low level output voltage VOL 6 35 mV VCC+ = 2.7 V, T = 25 °C 5
Output sink current Isink 12 22 mA VCC+ = 2.7 V, Vout = VCC, T = 25 °C 5
Output source current Isource 12 18 mA VCC+ = 2.7 V, Vout = 0 V, T = 25 °C 5
Supply current (per channel) ICC 30 51 µA VCC+ = 2.7 V, Vout = VCC/2, RL > 1 MΩ, T = 25 °C 5
Gain bandwidth product GBP 0.62 1 MHz VCC+ = 2.7 V, RL = 10 kΩ, CL = 100 pF 5
Input offset voltage (TSV52xA) Vio 600 µV VCC+ = 3.3 V, T = 25 °C 6
Input offset voltage (TSV52xA) Vio 2400 µV VCC+ = 3.3 V, -40 °C < T < 125 °C 6
Input offset current Iio 1 10 pA VCC+ = 3.3 V, Vout = VCC/2, T = 25 °C 6
Input bias current Iib 1 10 pA VCC+ = 3.3 V, Vout = VCC/2, T = 25 °C 6
Common-mode rejection ratio CMR 51 73 dB VCC+ = 3.3 V, Vic = -0.1 V to VCC +0.1 V, Vout = VCC/2, RL = 1 MΩ, T = 25 °C 6
Large signal voltage gain Avd 91 106 VCC+ = 3.3 V, Vout = 0.5 V to (VCC - 0.5 V), RL = 1 MΩ, T = 25 °C 6
High level output voltage VOH 3 35 mV VCC+ = 3.3 V, T = 25 °C 6
Low level output voltage VOL 7 35 mV VCC+ = 3.3 V, T = 25 °C 6
Output sink current Isink 20 31 mA VCC+ = 3.3 V, Vout = VCC, T = 25 °C 6
Output source current Isource 19 27 mA VCC+ = 3.3 V, Vout = 0 V, T = 25 °C 6
Supply current (per channel) ICC 32 55 µA VCC+ = 3.3 V, Vout = VCC/2, RL > 1 MΩ, T = 25 °C 6
Gain bandwidth product GBP 0.64 1 MHz VCC+ = 3.3 V, RL = 10 kΩ, CL = 100 pF 7
Thermal resistance junction-to-ambient Rthja 205 °C/W SC70-5 package, junction-to-ambient; typical value 4

CAD (KiCad official)

  • Symbol: TSV521AICT
  • Footprint: Package_TO_SOT_SMD:SOT-353_SC-70-5
  • 3D model: SC-70-5 (KiCad packages3D, STEP)
  • 3D model files: tsv521aict-etched.step / tsv521aict-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tsv521aict.step / tsv521aict.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (27 pp, sha256 f943e62c5e69a0ca, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF