component
CM1351-LAT
Public Made by Adomby adom
iCM(创芯微) , TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCM1351-LAT
iCM(创芯微) · IC · TSSOP-16
CM1351-LAT from iCM(创芯微), in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC | power_in | Positive supply input and battery 1 positive connection; absolute maximum VCC is VSS-0.3 V to VSS+40 V, and VSS should be connected before VCC. |
| 2 | VNC | passive | Labeled VNC in the pin table but described as a battery 1 positive voltage connection; no electrical limit is stated for this pin. |
| 3 | VNC | passive | Labeled VNC in the pin table but described as a battery 1 positive voltage connection; no electrical limit is stated for this pin. |
| 4 | VC1 | input | Battery 1 positive voltage sense connection; cell input absolute maximum is VSS-0.3 V to VSS+40 V. |
| 5 | VC2 | input | Battery 1 negative voltage and battery 2 positive voltage sense connection; cell input absolute maximum is VSS-0.3 V to VSS+40 V. |
| 6 | VC3 | input | Battery 2 negative voltage and battery 3 positive voltage sense connection; cell input absolute maximum is VSS-0.3 V to VSS+40 V. |
| 7 | VC4 | input | Battery 3 negative voltage and battery 4 positive voltage sense connection; cell input absolute maximum is VSS-0.3 V to VSS+40 V. |
| 8 | VC5 | input | Battery 4 negative voltage and battery 5 positive voltage sense connection; cell input absolute maximum is VSS-0.3 V to VSS+40 V. |
| 9 | VSS | power_in | Chip ground and battery 5 negative connection; reference for all absolute maximum ratings. |
| 10 | TEC | passive | Discharge overcurrent delay adjustment pin, set by external capacitor CTEC; absolute maximum is VSS-0.3 V to VSS+5.5 V. |
| 11 | RTS | input | Connects to the NTC thermistor for temperature detection; absolute maximum is VSS-0.3 V to VCC+0.3 V. |
| 12 | RTV | passive | Connects to a resistor to RTS that sets the protection temperature; absolute maximum is VSS-0.3 V to VSS+5.5 V. |
| 13 | VINI | input | Overcurrent detection input sensing the discharge/charge current voltage; absolute maximum is VSS-0.3 V to VCC+0.3 V. |
| 14 | DO | output | Discharge MOSFET control output; absolute maximum is VSS-0.3 V to VCC+0.3 V, with high level about VCC-0.7 V (10.8 V typical when VCC>12 V) and low level at VSS. |
| 15 | CO | output | Charge MOSFET control output; absolute maximum is VSS-15 V to VCC+0.3 V, with high level about VCC-0.7 V (10.8 V typical when VCC>12 V) and low level Hi-Z. |
| 16 | VM | input | Charger and load detection pin; absolute maximum is VSS-15 V to VCC+0.3 V, with about 50 kΩ internal resistance to VSS. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | iCM(创芯微) |
| Package | TSSOP-16 |
| Category | |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Absolute max: power supply voltage VCC (VCC pin, referenced to VSS) | VCC | -0.3 | 40 | V | Printed as VSS-0.3 ~ VSS+40 V; min/max are offsets from VSS | 6 | |
| Absolute max: cell input voltage VCn (VC1-VC5) | VCELL | -0.3 | 40 | V | Printed as VSS-0.3 ~ VSS+40 V (n=1~5); min/max are offsets from VSS | 6 | |
| Absolute max: input voltage 1 (RTV, TEC) | VIN1 | -0.3 | 5.5 | V | Printed as VSS-0.3 ~ VSS+5.5 V; referenced to VSS | 6 | |
| Absolute max: input voltage 2 (VM, CO) | VIN2 | -15 | 0.3 | V | Printed as VSS-15 ~ VCC+0.3 V; min offset from VSS, max offset from VCC | 6 | |
| Absolute max: input voltage 3 (DO, RTS, VINI) | VIN3 | -0.3 | 0.3 | V | Printed as VSS-0.3 ~ VCC+0.3 V; min offset from VSS, max offset from VCC | 6 | |
| Absolute max: operating ambient temperature TOPR | TOPR | -40 | 85 | °C | 6 | ||
| Absolute max: storage temperature range TSTG | TSTG | -55 | 125 | °C | 6 | ||
| Normal operating current (25°C table) | IVCC | 10 | 15 | μA | VCn - VCn+1 = 3.5V, VC5-VSS = 3.5V | 7 | |
| Overcharge protection delay TOC | TOC | 0.7 | 1 | 1.3 | s | VCn - VCn+1 = 3.5V, VC5-VSS = 3.5 → 4.4V | 7 |
| Overcharge release delay TOCR | TOCR | 128 | 256 | 384 | ms | VCn - VCn+1 = 3.5V, VC5-VSS = 4.4 → 3.5V | 7 |
| Overdischarge release voltage VODR (25°C, ±80 mV) for CM1351-LAT (nominal 3.000 V) | VODR | -0.08 | 3 | 0.08 | V | VCn - VCn+1 = 3.5V, VC5-VSS = 2.0 → 3.5V | 7 |
| Overdischarge protection delay TOD | TOD | 0.7 | 1 | 1.3 | s | VCn - VCn+1 = 3.5V, VC5-VSS = 3.5 → 2.0V | 7 |
| Overdischarge release delay TODR | TODR | 128 | 256 | 384 | ms | VCn - VCn+1 = 3.5V, VC5-VSS = 2.0 → 3.5V | 7 |
| Low-voltage charge inhibit voltage VLV | VLV | 1.2 | 1.5 | 1.8 | V | VCn - VCn+1 = 3.5V, VC5-VSS = 3.5 → 1.2V | 7 |
| Low-voltage charge inhibit release voltage VLVR | VLVR | 1.22 | 1.52 | 1.82 | V | VCn - VCn+1 = 3.5V, VC5-VSS = 1.2 → 3.5V | 7 |
| Low-voltage charge inhibit delay TLV | TLV | 0.7 | 1 | 1.3 | s | VCn - VCn+1 = 3.5V, VC5-VSS = 3.5 → 1.2V | 7 |
| Low-voltage charge inhibit release delay TLVR | TLVR | 128 | 256 | 384 | ms | VCn - VCn+1 = 3.5V, VC5-VSS = 1.2 → 3.5V | 7 |
| Discharge overcurrent 1 protection voltage VEC1 (25°C, ±5 mV) for CM1351-LAT (nominal 0.050 V) | VEC1 | -0.005 | 0.05 | 0.005 | V | VCn - VCn+1 = 3.5V, VC5-VSS = 3.5V, VINI = 0 → 0.18V | 7 |
| Discharge overcurrent 1 protection delay TEC1 | TEC1 | 0.5 | 1 | 1.5 | s | VCn - VCn+1 = 3.5V, VC5-VSS = 3.5V, VINI = 0 → 0.18V, CTEC=0.1μF | 7 |
| Discharge overcurrent 2 protection voltage VEC2 (±15% of VEC2; nominal 0.100 V for CM1351-LAT per table 1) | VEC2 | -15 | 15 | % | VCn - VCn+1 = 3.5V, VC5-VSS = 3.5V, VINI = 0 → 0.35V | 7 | |
| Discharge overcurrent 2 protection delay TEC2 | TEC2 | 50 | 100 | 150 | ms | VCn - VCn+1 = 3.5V, VC5-VSS = 3.5V, VINI = 0 → 0.35V, CTEC=0.1μF | 7 |
| Short-circuit protection delay TSHORT | TSHORT | 100 | 300 | 500 | μs | VCn - VCn+1 = 3.5V, VC5-VSS = 3.5V, VINI = 0 → 0.8V | 8 |
| Discharge overcurrent release delay TECR | TECR | 22 | 32 | 42 | ms | VCn - VCn+1 = 3.5V, VC5-VSS = 3.5V, VINI = 0.8 → 0V | 8 |
| Charge overcurrent protection delay TCHA | TCHA | 180 | 256 | 332 | ms | VCn - VCn+1 = 3.5V, VC5-VSS = 3.5V, VINI = 0 → -1.0V | 8 |
| Charge overcurrent release delay TCHAR | TCHAR | 45 | 64 | 83 | ms | VCn - VCn+1 = 3.5V, VC5-VSS = 3.5V, VINI = -1V → 0V | 8 |
| Wire-break protection delay TOW | TOW | 4 | s | CVC1~5=0.1μF | 8 | ||
| Charge high-temperature protection temperature TCH (±3 °C; nominal set by RT) | TCH | -3 | 3 | °C | VCn - VCn+1 = 3.5V, VC5-VSS = 3.5V, RNTC = 100k → 10k | 8 | |
| Charge high-temperature release temperature TCHR (±3 °C; nominal set by RT) | TCHR | -3 | 3 | °C | VCn - VCn+1 = 3.5V, VC5-VSS = 3.5V, RNTC = 10k → 100k | 8 | |
| Discharge high-temperature protection temperature TDH (±3 °C; nominal set by RT) | TDH | -3 | 3 | °C | VCn - VCn+1 = 3.5V, VC5-VSS = 3.5V, RNTC = 100k → 10k | 8 | |
| Discharge high-temperature release temperature TDHR (±3 °C; nominal set by RT) | TDHR | -3 | 3 | °C | VCn - VCn+1 = 3.5V, VC5-VSS = 3.5V, RNTC = 10k → 100k | 8 | |
| Charge high-temperature protection delay DTCH | DTCH | 0.7 | 1 | 1.3 | s | VCn - VCn+1 = 3.5V, VC5-VSS = 3.5V, RNTC = 100k → 10k | 8 |
| Charge high-temperature release delay DTCHR | DTCHR | 90 | 128 | 166 | ms | VCn - VCn+1 = 3.5V, VC5-VSS = 3.5V, RNTC = 10k → 100k | 8 |
| Discharge high-temperature protection delay DTDH | DTDH | 0.7 | 1 | 1.3 | s | VCn - VCn+1 = 3.5V, VC5-VSS = 3.5V, RNTC = 100k → 10k | 8 |
| Discharge high-temperature release delay DTDHR | DTDHR | 90 | 128 | 166 | ms | VCn - VCn+1 = 3.5V, VC5-VSS = 3.5V, RNTC = 10k → 100k | 8 |
| Charge low-temperature protection temperature TCL (±3 °C; nominal set by RNTC/RT configuration) | TCL | -3 | 3 | °C | VCn - VCn+1 = 3.5V, VC5-VSS = 3.5V, RNTC = 100k → 3M | 8 | |
| Charge low-temperature release temperature TCLR (±3 °C) | TCLR | -3 | 3 | °C | VCn - VCn+1 = 3.5V, VC5-VSS = 3.5V, RNTC = 3M → 100k | 8 | |
| Discharge low-temperature protection temperature TDL (±3 °C) | TDL | -3 | 3 | °C | VCn - VCn+1 = 3.5V, VC5-VSS = 3.5V, RNTC = 100k → 3M | 8 | |
| Discharge low-temperature release temperature TDLR (±3 °C) | TDLR | -3 | 3 | °C | VCn - VCn+1 = 3.5V, VC5-VSS = 3.5V, RNTC = 3M → 100k | 9 | |
| Charge low-temperature protection delay DTCL | DTCL | 0.7 | 1 | 1.3 | s | VCn - VCn+1 = 3.5V, VC5-VSS = 3.5V, RNTC = 100k → 3M | 9 |
| Charge low-temperature release delay DTCLR | DTCLR | 90 | 128 | 166 | ms | VCn - VCn+1 = 3.5V, VC5-VSS = 3.5V, RNTC = 3M → 100k | 9 |
| Discharge low-temperature protection delay DTDL | DTDL | 0.7 | 1 | 1.3 | s | VCn - VCn+1 = 3.5V, VC5-VSS = 3.5V, RNTC = 100k → 3M | 9 |
| Discharge low-temperature release delay DTDLR | DTDLR | 90 | 128 | 166 | ms | VCn - VCn+1 = 3.5V, VC5-VSS = 3.5V, RNTC = 3M → 100k | 9 |
| Discharge state detection voltage VSTS | VSTS | 1 | 4 | 7 | mV | VCn - VCn+1 = 3.5V, VC5-VSS = 3.5V, VINI = 0 → 10mV | 9 |
| Discharge state detection delay TSTS | TSTS | 3 | 4.5 | 6 | ms | VCn - VCn+1 = 3.5V, VC5-VSS = 3.5V, VINI = 0 → 10mV | 9 |
| Sleep entry delay TSLP | TSLP | 22 | 32 | 42 | s | VCn - VCn+1 = 3.5V, VC5-VSS = 3.5 → 1.5V | 9 |
CAD (KiCad official)
- Symbol:
CM1351-LAT - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
cm1351-lat-etched.step/cm1351-lat-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cm1351-lat.step/cm1351-lat.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: iCM(创芯微) datasheet (21 pp, sha256
9cc8ed7471336dab, retrieved 2026-10-17, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).