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FD2203S

Public Made by Adom

by adom

Fortior Tech Gate Drivers, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

markdown

FD2203S

Fortior Tech · Gate Drivers · SO-8

FD2203S from Fortior Tech, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VCC power_in Low-side supply voltage, recommended 8 V to 20 V referenced to COM, with absolute maximum -0.3 V to 25 V and UVLO trip at 6.3 V to 7.5 V.
2 HIN input High-side logic input (in phase with HO), with VIH minimum 2.4 V, VIL maximum 0.8 V, and a recommended range of 0 V to VCC.
3 LIN* input Low-side logic input (inverted at LO), with VIH minimum 2.4 V, VIL maximum 0.8 V, and a recommended range of 0 V to VCC.
4 COM power_in Ground reference for all pins; all voltage ratings in the datasheet are referenced to COM.
5 LO output Low-side gate drive output, swinging between 0 V and VCC, with low-level output short-circuit pulse current of 1.6 A minimum and 2.3 A typical (PWD ≤ 10 µs).
6 VS power_in High-side floating offset voltage, recommended -2 V to 250 V referenced to COM, with dVS/dt limited to 50 V/ns and static negative voltage of -6.0 V typical.
7 HO output High-side gate drive output, referenced to VS and swinging between VS and VB, with high-level output short-circuit pulse current of 1.1 A minimum and 1.6 A typical (PWD ≤ 10 µs).
8 VB power_in High-side floating supply voltage, recommended VS+8 V to VS+20 V, with absolute maximum of 275 V referenced to COM and UVLO trip at 6.3 V to 7.5 V.

Key specifications

Parameter Value
Manufacturer Fortior Tech
Package SO-8
Category Motor Driver ICs
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
High-level input threshold voltage VIH 2.4 V 3
Low-level input threshold voltage VIL 0.8 V 3
VCC undervoltage trip voltage (rising) VCCUV+ 6.3 6.9 7.5 V 3
VCC undervoltage reset voltage (falling) VCCUV- 5.9 6.5 7.1 V 3
VCC undervoltage hysteresis voltage VCCUVH 0.2 0.4 V 3
VBS undervoltage trip voltage (rising) VBSUV+ 6.3 6.9 7.5 V 3
VBS undervoltage reset voltage (falling) VBSUV- 5.9 6.5 7.1 V 3
VBS undervoltage hysteresis voltage VBSUVH 0.2 0.4 V 3
Floating supply leakage current ILK 1 10 μA VB=VS=250V 3
VBS quiescent current IQBS 140 250 μA VIN=0V 或 5V 3
VBS dynamic current IPBS 140 250 μA fHIN=20kHz 3
VCC quiescent current IQCC 460 700 uA VIN =0V 或 5V 3
VCC dynamic current IPCC 460 700 μA fIN=20kHz 3
LIN* high-level input bias current ILIN+ 20 40 μA VLIN*=0V 3
LIN* low-level input bias current ILIN- 2 μA VLIN*=5V 3
HIN high-level input bias current IHIN+ 20 40 μA VHIN=5V 3
HIN low-level input bias current IHIN- 2 μA VHIN=0V 3
High-level output voltage VOH 0.09 0.16 V IO=20mA 3
Low-level output voltage VOL 0.03 0.06 V IO=20mA 3
High-level output short-circuit pulsed current IOH 1.1 1.6 A VO=0V，PWD≤10μs 3
Low-level output short-circuit pulsed current IOL 1.6 2.3 A VO=15V，PWD≤10μs 3
Output rising-edge propagation delay ton 350 520 ns CL=1000pF 3
Output falling-edge propagation delay toff 100 150 ns CL=1000pF 3
Output rise time tr 12 ns CL=1000pF 3
Output fall time tf 8 ns CL=1000pF 3
Dead time DT 250 370 ns 3
High/low-side propagation delay matching MT 50 ns 3
High-side floating offset voltage VS -2 250 V 2
Low-side supply voltage VCC 8 20 V 2
Low-side output voltage VLO 0 V 2
Logic input voltage (HIN, LIN*) VIN 0 V 2
Ambient temperature TA -40 125 °C 2
High-side floating absolute voltage VB -0.3 275 V 2
Low-side supply voltage VCC -0.3 25 V 2
Low-side output voltage VLO -0.3 V 2
Logic input voltage (HIN, LIN*) VIN -0.3 V 2
Allowable offset voltage slew rate dVS/dt 50 V/ns 2
Power dissipation SOIC-8 PD 0.625 W TA≤25C 2
Junction-to-ambient thermal resistance SOIC-8 RthJA 200 C/W SOIC-8 2
Junction temperature range Tj 150 C 2
Storage temperature range Tstg -55 150 C 2
VS static negative voltage VSN -6 V 3

CAD (KiCad official)

  • Symbol: FD2203S
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SO-8 (KiCad packages3D, STEP)
  • 3D model files: fd2203s-etched.step / fd2203s-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); fd2203s.step / fd2203s.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Fortior Tech datasheet (8 pp, sha256 87f93aebe8a0f921, retrieved 2026-10-19, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF