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AD7741BRZ

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Analog Devices Voltage-to-Frequency / Frequency-to-Voltage Converters, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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AD7741BRZ

Analog Devices · Voltage-to-Frequency / Frequency-to-Voltage Converters · SO-8

AD7741BRZ from Analog Devices, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD power_in Power supply input operated from +4.75 V to +5.25 V, which should be adequately decoupled to GND.
2 GND power_in Ground reference point for all circuitry on the part.
3 CLKOUT output External clock output that connects to the crystal with CLKIN, or provides an inverted clock when an external clock drives CLKIN; it should be buffered if used elsewhere and loaded with no more than one CMOS load.
4 CLKIN input Master clock input driven by a crystal across CLKIN and CLKOUT or by a CMOS-compatible external clock with CLKOUT left unconnected, at up to 6 MHz.
5 REFIN/OUT bidirectional Reference input to the VFC core that sets its span; left unconnected it uses the internal 2.5 V reference, or a precision external reference (e.g., REF192) can overdrive it.
6 VIN power_in Buffered analog input to the VFC with an input range from 0 V to VREF that draws virtually no current from the source.
7 PD input Active-low power-down input; when low the part enters power-down mode and typically consumes 15 µA.
8 fOUT output Frequency output of the synchronous VFC.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package SO-8
Category Data Converters
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Integral Nonlinearity INL -0.012 0.012 % of Span fCLKIN = 200 kHz 2
Integral Nonlinearity INL -0.024 0.024 % of Span fCLKIN = 6.144 MHz, VDD > 4.8 V 2
Offset Error -40 40 mV 2
Gain Error 0 0.8 1.6 % of Span 2
Offset Error Drift -30 30 µV/°C 2
Gain Error Drift -16 16 ppm of Span/°C 2
Power Supply Rejection Ratio PSRR -63 dB ∆VDD = ±5% 2
Analog Input Current -100 50 100 nA 2
Analog Input Voltage Range VIN 0 V 0 to VREF 2
REFOUT Output Voltage 2.38 2.5 2.6 V 2
REFOUT Output Impedance 1 kΩ 2
Reference Drift -50 50 ppm/°C 2
Line Rejection -60 dB 2
Reference Noise 100 µV p-p 0.1 Hz to 10 Hz 2
Output High Voltage VOH 4 V Output Sourcing 800 µA 2
Output Low Voltage VOL 0.4 V Output Sinking 1.6 mA 2
PD Input High Voltage VIH 2.4 V 2
PD Input Low Voltage VIL 0.8 V 2
PD Input Current -100 100 nA 2
PD Pin Capacitance 6 10 pF 2
CLKIN Input High Voltage VIH 3.5 V 2
CLKIN Input Low Voltage VIL 0.8 V 2
CLKIN Input Current -2 2 µA 2
CLKIN Pin Capacitance 6 10 pF 2
Supply Voltage VDD 4.75 5.25 V 2
IDD (Normal Mode) IDD 8 mA Output Unloaded 2
IDD (Power-Down) IDD 15 35 µA 2
Power-Up Time 30 µs Coming Out of Power-Down Mode 2
Input Clock Frequency fCLKIN 6.144 MHz For Specified Performance 2
Minimum Output Frequency 0.05 Hz VIN = 0 V; printed as 0.05 fCLKIN 2
Maximum Output Frequency 0.45 Hz VIN = VREF; printed as 0.45 fCLKIN 2
Maximum Clock Frequency fCLKIN 6.144 MHz B and Y Version 4
Input Clock Mark/Space Ratio (tHIGH/tLOW) tHIGH/tLOW 45 55 55/45 max, 45/55 min 4
CLKIN rising edge to fOUT rising edge t1 9 ns 4
fOUT Rise Time t2 4 ns 4
fOUT Fall Time t3 4 ns 4
VDD to GND VDD -0.3 7 V TA = +25°C 4
Analog Input Voltage to GND -5 V max is VDD + 0.3 V 4
Digital Input Voltage to GND -0.3 V max is VDD + 0.3 V 4
Reference Input Voltage to GND -0.3 V max is VDD + 0.3 V 4
fOUT to GND -0.3 V max is VDD + 0.3 V 4
Operating Temperature Range (Industrial, B Version) -40 85 °C 4
Storage Temperature Range -65 150 °C 4
Junction Temperature 150 °C 4
Power Dissipation (SOIC) 450 mW SOIC Package 4
Thermal Impedance (8 Lead SOIC) θJA 157 °C/W SOIC Package, 8 Lead 4
Lead Temperature, Soldering Vapor Phase 215 °C 60 sec 4
Lead Temperature, Soldering Infrared 220 °C 15 sec 4

CAD (KiCad official)

  • Symbol: AD7741BRZ
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SO-8 (KiCad packages3D, STEP)
  • 3D model files: ad7741brz-etched.step / ad7741brz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad7741brz.step / ad7741brz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (12 pp, sha256 9ed3fb9faa02b73a, retrieved 2026-10-26, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF