Loads on click. Unloads only if this page sits in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads on click. Unloads only if this page sits in the background.

PCB Footprint

Open full view ↗
Loads on click. Unloads only if this page sits in the background.
Loads on click. Unloads only if this page sits in the background.
Download PDF
Contents

README

markdown

UC3526DWTR

Texas Instruments · DC-DC Controllers · SOIC-18-300mil

UC3526DWTR from Texas Instruments, in a SOIC-18-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 +Error input Non-inverting input of the transconductance error amplifier, with input common-mode range of 0 to +5.2V.
2 -Error input Inverting input of the error amplifier, used with +Error for the voltage feedback connection to the supply output.
3 Comp output Error amplifier output (2MΩ output impedance) where loop compensation is connected as shunt reactance to ground, feeding the PWM comparator.
4 Css passive Soft-start capacitor connection, charged by an internal 100µA current source after RESET goes HIGH and held discharged during undervoltage lockout.
5 Reset bidirectional Active-LOW TTL/CMOS-compatible digital port that discharges the soft-start capacitor when held LOW and is held LOW by undervoltage lockout.
6 -Current Sense input Inverting input of the current limit comparator, with a typical 100mV sense voltage threshold.
7 +Current Sense input Non-inverting input of the current limit comparator, with a typical 100mV sense voltage threshold.
8 Shutdown bidirectional Active-LOW TTL/CMOS-compatible digital port that immediately inhibits all PWM output pulses when pulled LOW.
9 RTIMING passive Oscillator timing resistor connection, with recommended RT of 2kΩ to 150kΩ.
10 CT passive Oscillator timing capacitor connection (recommended 1nF to 20µF) that carries the sawtooth waveform and is tied together across devices for synchronization.
11 RD passive Deadtime setting resistor connection to ground, where a larger value adds dead time (400ns/Ω at 40kHz) and 0Ω gives minimum dead time.
12 Sync bidirectional Active-LOW TTL/CMOS-compatible digital port that initiates an oscillator discharge cycle when driven LOW and provides the logic clock for synchronizing multiple devices.
13 Output A output Totem-pole output driver A that sources and sinks 100mA continuously (200mA peak) at half the oscillator frequency.
14 VC power_in Collector supply voltage for the output drivers, recommended +4.5V to +35V (absolute maximum +40V).
15 Ground power_in Ground connection for the device.
16 Output B output Totem-pole output driver B that sources and sinks 100mA continuously (200mA peak) at half the oscillator frequency.
17 +VIN power_in Input supply voltage, recommended +8V to +35V (absolute maximum +40V).
18 VREF power_out Temperature-compensated 5.0V reference output providing 0 to 20mA of load current.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-18-300mil
Category Power Supply Chip
Pins 18

CAD (KiCad official)

  • Symbol: UC3526DWTR
  • Footprint: Package_SO:SOIC-18W_7.5x11.6mm_P1.27mm
  • 3D model: SOIC-18-300mil (KiCad packages3D, STEP)
  • 3D model files: uc3526dwtr-etched.step / uc3526dwtr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); uc3526dwtr.step / uc3526dwtr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (11 pp, sha256 610c26f9ef74514c, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF