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TMS320F28016PZS

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Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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TMS320F28016PZS

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)

TMS320F28016PZS from Texas Instruments, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GPIO12/TZ1 bidirectional General-purpose input/output 12 (I/O/Z) with pullup enabled at reset; alternates are Trip Zone input 1 (I), CAN-B transmit (O) and SPI-B slave in/master out (I/O).
2 VSS power_in Digital ground pin.
3 VDDIO power_in Digital I/O power pin, 3.3 V.
4 GPIO29/SCITXDA/TZ6 bidirectional General-purpose input/output 29 (I/O/Z) with an 8-mA typical output buffer; alternates are SCI-A transmit data (O) and Trip Zone 6 input (I).
5 GPIO33/SCLA/EPWMSYNCO/ADCSOCBO bidirectional General-purpose input/output 33 (I/O/Z) with pullup enabled at reset; alternates are I2C clock open-drain (I/OD), EPWM external sync output (O) and ADC start-of-conversion B output (O).
6 GPIO30/CANRXA bidirectional General-purpose input/output 30 (I/O/Z) with an 8-mA typical output buffer; alternate is Enhanced CAN-A receive data (I).
7 GPIO31/CANTXA bidirectional General-purpose input/output 31 (I/O/Z) with an 8-mA typical output buffer; alternate is Enhanced CAN-A transmit data (O).
8 GPIO14/TZ3 bidirectional General-purpose input/output 14 (I/O/Z) with pullup enabled at reset; alternates are Trip Zone input 3 (I), SCI-B transmit (O) and SPI-B clock (I/O).
9 GPIO15/TZ4 bidirectional General-purpose input/output 15 (I/O/Z) with pullup enabled at reset; alternates are Trip Zone input 4 (I), SCI-B receive (I) and SPI-B slave transmit enable (I/O).
10 VDD power_in CPU and logic digital power pin, 1.8 V.
11 VSS power_in Digital ground pin.
12 VDD1A18 power_in ADC analog power pin, 1.8 V.
13 VSS1AGND power_in ADC analog ground pin.
14 VSSA2 power_in ADC analog ground pin.
15 VDDA2 power_in ADC analog power pin, 3.3 V.
16 ADCINA7 input ADC Group A, channel 7 analog input, 0 to 3 V with respect to ADCLO.
17 ADCINA6 input ADC Group A, channel 6 analog input, 0 to 3 V with respect to ADCLO.
18 ADCINA5 input ADC Group A, channel 5 analog input, 0 to 3 V with respect to ADCLO.
19 ADCINA4 input ADC Group A, channel 4 analog input, 0 to 3 V with respect to ADCLO.
20 ADCINA3 input ADC Group A, channel 3 analog input, 0 to 3 V with respect to ADCLO.
21 ADCINA2 input ADC Group A, channel 2 analog input, 0 to 3 V with respect to ADCLO.
22 ADCINA1 input ADC Group A, channel 1 analog input, 0 to 3 V with respect to ADCLO.
23 ADCINA0 input ADC Group A, channel 0 analog input, 0 to 3 V with respect to ADCLO.
24 ADCLO input ADC low reference; connect to analog ground.
25 VSSAIO power_in ADC analog I/O ground pin.
26 VDDAIO power_in ADC analog I/O power pin, 3.3 V.
27 ADCINB0 input ADC Group B, channel 0 analog input, 0 to 3 V with respect to ADCLO.
28 ADCINB1 input ADC Group B, channel 1 analog input, 0 to 3 V with respect to ADCLO.
29 ADCINB2 input ADC Group B, channel 2 analog input, 0 to 3 V with respect to ADCLO.
30 ADCINB3 input ADC Group B, channel 3 analog input, 0 to 3 V with respect to ADCLO.
31 ADCINB4 input ADC Group B, channel 4 analog input, 0 to 3 V with respect to ADCLO.
32 ADCINB5 input ADC Group B, channel 5 analog input, 0 to 3 V with respect to ADCLO.
33 ADCINB6 input ADC Group B, channel 6 analog input, 0 to 3 V with respect to ADCLO.
34 ADCINB7 input ADC Group B, channel 7 analog input, 0 to 3 V with respect to ADCLO.
35 ADCREFIN input External ADC reference input.
36 ADCREFM output Internal ADC reference medium output; requires a 2.2 µF ceramic bypass capacitor with ESR under 1.5 Ω to analog ground and should not be loaded externally.
37 ADCREFP output Internal ADC reference positive output; requires a 2.2 µF ceramic bypass capacitor with ESR under 1.5 Ω to analog ground and should not be loaded externally.
38 ADCRESEXT passive ADC external current bias resistor; connect a 22-kΩ resistor to analog ground.
39 VSS2AGND power_in ADC analog ground pin.
40 VDD2A18 power_in ADC analog power pin, 1.8 V.
41 VSS power_in Digital ground pin.
42 VDD power_in CPU and logic digital power pin, 1.8 V.
43 GPIO34 bidirectional General-purpose input/output 34 (I/O/Z) with pullup enabled at reset; no peripheral alternate function is listed.
44 GPIO1/EPWM1B bidirectional General-purpose input/output 1 (I/O/Z) with pullup not enabled at reset; alternate is Enhanced PWM1 output B (O).
45 GPIO2/EPWM2A bidirectional General-purpose input/output 2 (I/O/Z) with pullup not enabled at reset; alternate is Enhanced PWM2 output A and HRPWM channel (O).
46 VDDIO power_in Digital I/O power pin, 3.3 V.
47 GPIO0/EPWM1A bidirectional General-purpose input/output 0 (I/O/Z) with pullup not enabled at reset; alternate is Enhanced PWM1 output A and HRPWM channel (O).
48 GPIO3/EPWM2B bidirectional General-purpose input/output 3 (I/O/Z) with pullup not enabled at reset; alternate is Enhanced PWM2 output B (O).
49 VSS power_in Digital ground pin.
50 GPIO16/SPISIMOA/TZ5 bidirectional General-purpose input/output 16 (I/O/Z) with pullup enabled at reset; alternates are SPI-A slave in/master out (I/O), enhanced CAN-B transmit (O) and Trip Zone input 5 (I).
51 GPIO4/EPWM3A bidirectional General-purpose input/output 4 (I/O/Z) with pullup not enabled at reset; alternate is Enhanced PWM3 output A and HRPWM channel (O).
52 GPIO17/SPISOMIA/TZ6 bidirectional General-purpose input/output 17 (I/O/Z) with pullup enabled at reset; alternates are SPI-A slave out/master in (I/O) and Trip Zone input 6 (I).
53 GPIO5/EPWM3B/ECAP1 bidirectional General-purpose input/output 5 (I/O/Z) with pullup not enabled at reset; alternates are Enhanced PWM3 output B (O) and enhanced capture 1 input/output (I/O).
54 GPIO18/SPICLKA bidirectional General-purpose input/output 18 (I/O/Z) with pullup enabled at reset; alternates are SPI-A clock (I/O) and SCI-B transmit (O).
55 VSS power_in Digital ground pin.
56 GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO bidirectional General-purpose input/output 6 (I/O/Z) with pullup not enabled at reset; alternates are Enhanced PWM4 output A (O), external ePWM sync pulse input (I) and sync pulse output (O).
57 GPIO19/SPISTEA bidirectional General-purpose input/output 19 (I/O/Z) with pullup enabled at reset; alternates are SPI-A slave transmit enable (I/O) and SCI-B receive (I).
58 GPIO7/EPWM4B/ECAP2 bidirectional General-purpose input/output 7 (I/O/Z) with pullup not enabled at reset; alternates are Enhanced PWM4 output B (O) and enhanced capture 2 input/output (I/O).
59 VDD power_in CPU and logic digital power pin, 1.8 V.
60 GPIO8/ADCSOCAO bidirectional General-purpose input/output 8 (I/O/Z) with pullup not enabled at reset; alternate is ADC start-of-conversion A output (O).
61 GPIO9 bidirectional General-purpose input/output 9 (I/O/Z) with pullup not enabled at reset; alternates are Enhanced PWM5 output B (O), SCI-B transmit (O) and enhanced capture 3 input/output (I/O).
62 VSS power_in Digital ground pin.
63 GPIO20 bidirectional General-purpose input/output 20 (I/O/Z) with pullup enabled at reset; alternates are enhanced QEP1 input A (I), SPI-C slave in/master out (I/O) and enhanced CAN-B transmit (O).
64 GPIO10/ADCSOCBO bidirectional General-purpose input/output 10 (I/O/Z) with pullup not enabled at reset; alternates are Enhanced PWM6 output A (O), enhanced CAN-B receive (I) and ADC start-of-conversion B output (O).
65 VDDIO power_in Digital I/O power pin, 3.3 V.
66 XCLKOUT output Output clock derived from SYSCLKOUT at the same, one-half or one-quarter frequency (XCLKOUTDIV); reset value is SYSCLKOUT/4 and it is not placed in high-impedance during reset (O/Z, 8 mA drive).
67 GPIO21 bidirectional General-purpose input/output 21 (I/O/Z) with pullup enabled at reset; alternates are enhanced QEP1 input B (I), SPI-C master in/slave out (I/O) and enhanced CAN-B receive (I).
68 VDD power_in CPU and logic digital power pin, 1.8 V.
69 VSS power_in Digital ground pin.
70 GPIO11/EPWM6B/SCIRXDB/ECAP4 bidirectional General-purpose input/output 11 (I/O/Z) with pullup not enabled at reset; alternates are Enhanced PWM6 output B (O), SCI-B receive (I) and enhanced capture 4 input/output (I/O).
71 GPIO22/EQEP1S/SPICLKC/SCITXDB bidirectional General-purpose input/output 22 (I/O/Z) with pullup enabled at reset; alternates are enhanced QEP1 strobe (I/O), SPI-C clock (I/O) and SCI-B transmit (O).
72 GPIO23/EQEP1I/SPISTEC/SCIRXDB bidirectional General-purpose input/output 23 (I/O/Z) with pullup enabled at reset; alternates are enhanced QEP1 index (I/O), SPI-C slave transmit enable (I/O) and SCI-B receive (I).
73 TDI input JTAG test data input with internal pullup; TDI is clocked into the selected register on a rising edge of TCK.
74 TMS input JTAG test-mode select with internal pullup; clocked into the TAP controller on the rising edge of TCK.
75 TCK input JTAG test clock with internal pullup.
76 TDO output JTAG scan test data output; shifted out on the falling edge of TCK (O/Z, 8 mA drive).
77 VSS power_in Digital ground pin.
78 XRS bidirectional Device reset input and watchdog reset output; open-drain output with internal pullup that is driven low for 512 OSCCLK cycles during a watchdog reset, and external drivers must be open-drain.
79 GPIO27/ECAP4/EQEP2S/SPISTEB bidirectional General-purpose input/output 27 (I/O/Z) with pullup enabled at reset; alternates are enhanced capture 4 (I/O), enhanced QEP2 strobe (I/O) and SPI-B slave transmit enable (I/O).
80 EMU0 bidirectional Emulator pin 0 (I/O/Z, 8 mA drive, pullup); an external 2.2-kΩ to 4.7-kΩ pullup is recommended, and EMU0 high with EMU1 low latches boundary-scan mode on a rising edge of TRST.
81 EMU1 bidirectional Emulator pin 1 (I/O/Z, 8 mA drive, pullup); an external 2.2-kΩ to 4.7-kΩ pullup is recommended for debugger operation.
82 VDDIO power_in Digital I/O power pin, 3.3 V.
83 GPIO24/ECAP1 bidirectional General-purpose input/output 24 (I/O/Z) with pullup enabled at reset; alternates are enhanced capture 1 (I/O), enhanced QEP2 input A (I) and SPI-B slave in/master out (I/O).
84 TRST input JTAG test reset with internal pulldown; it must be held low during normal operation and an external pulldown (about 2.2 kΩ generally adequate) is required.
85 VDD power_in CPU and logic digital power pin, 1.8 V.
86 X2 output Internal oscillator output for a quartz crystal or ceramic resonator across X1 and X2; leave unconnected if not used.
87 VSS power_in Digital ground pin.
88 X1 input Internal/external oscillator input referenced to the 1.8 V core supply; tie to GND when a 3.3 V external oscillator is used on XCLKIN.
89 VSS power_in Digital ground pin.
90 XCLKIN input External oscillator input for a 3.3 V external clock; tie X1 to GND in this configuration.
91 GPIO25/ECAP2/EQEP2B/SPISOMIB bidirectional General-purpose input/output 25 (I/O/Z) with pullup enabled at reset; alternates are enhanced capture 2 (I/O), enhanced QEP2 input B (I) and SPI-B master in/slave out (I/O).
92 GPIO28/SCIRXDA/TZ5 bidirectional General-purpose input/output 28 (I/O/Z) with an 8-mA typical output buffer; alternates are SCI-A receive data (I) and Trip Zone input 5 (I).
93 VDD power_in CPU and logic digital power pin, 1.8 V.
94 VSS power_in Digital ground pin.
95 GPIO13/TZ2 bidirectional General-purpose input/output 13 (I/O/Z) with pullup enabled at reset; alternates are Trip Zone input 2 (I), enhanced CAN-B receive (I) and SPI-B slave out/master in (I/O).
96 VDD3VFL power_in 3.3-V flash core power pin that must be connected to 3.3 V at all times.
97 TEST1 unconnected Test pin reserved for TI; must be left unconnected.
98 TEST2 unconnected Test pin reserved for TI; must be left unconnected.
99 GPIO26/ECAP3/EQEP2I/SPICLKB bidirectional General-purpose input/output 26 (I/O/Z) with pullup enabled at reset; alternates are enhanced capture 3 (I/O), enhanced QEP2 index (I/O) and SPI-B clock (I/O).
100 GPIO32/SDAA/EPWMSYNCI/ADCSOCAO bidirectional General-purpose input/output 32 (I/O/Z) with pullup enabled at reset; alternates are I2C data open-drain (I/OD), external ePWM sync pulse input (I) and ADC start-of-conversion A output (O).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package LQFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

CAD (KiCad official)

  • Symbol: TMS320F28016PZS
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: tms320f28016pzs-etched.step / tms320f28016pzs-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tms320f28016pzs.step / tms320f28016pzs.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (157 pp, sha256 a13113c4c002c567, retrieved 2026-10-08, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF