TPS3305-18DGNR from Texas Instruments, in a MSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	SENSE1	input	Sense voltage input 1; RESET is asserted when this input falls below its threshold, which is 2.93 V typ for the TPS3305-18.
2	SENSE2	input	Sense voltage input 2; RESET is asserted when this input falls below its threshold, which is 1.68 V typ for the TPS3305-18.
3	WDI	input	Watchdog timer input; RESET is asserted if WDI is not toggled for more than 1.6 s typ, with VIH of 0.7 x VDD and VIL of 0.3 x VDD.
4	GND	power_in	Ground reference; all voltage ratings in the datasheet are stated with respect to GND.
5	RESET	output	Active-low reset output, asserted low when a SENSEn input is below its threshold, WDI times out, or MR is low.
6	RESET	output	Active-high reset output, the complement of the active-low RESET output.
7	MR	input	Manual reset input; driving MR low asserts RESET, with VIH of 0.7 x VDD and VIL of 0.3 x VDD.
8	VDD	power_in	Supply voltage input, specified from 2.7 V to 6 V, with RESET defined from VDD of 1.1 V and above.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	MSOP-8
Category	Power Management (PMIC)
Pins	8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage range (VDD input supply range)	VDD	2.7		6	V		3
Operating junction temperature range	TJ	-40		85	°C		3
Supply voltage range, absolute maximum	VDD	-0.3		7	V	All voltage values with respect to GND	2
Reset output voltage range, absolute maximum	VRESET, VRESET	-0.3		7	V		2
Maximum low output current	IOL			5	mA		2
Maximum high output current	IOH			-5	mA		2
Input clamp current	IIK	-20		20	mA	VI < 0 or VI > VDD	2
Output clamp current	IOK	-20		20	mA	VO < 0 or VO > VDD	2
Storage temperature range	Tstg	-65		150	°C		2
Soldering temperature				260	°C		2
Continuous total power dissipation, DGN package	PD			2.14	W	DGN package, TA ≤ +25°C	2
Power rating derating factor, DGN package			17.1		mW/°C	DGN package, above TA = +25°C	2
Negative-going input threshold voltage, SENSE1 (3.3V supervised)	VIT-	2.86	2.93	3	V	VDD = 2.7V to 6V, TA = 0°C to +85°C	3
Negative-going input threshold voltage, SENSE2 (1.8V supervised)	VIT-	1.64	1.68	1.72	V	VDD = 2.7V to 6V, TA = 0°C to +85°C	3
Negative-going input threshold voltage, SENSE1 (3.3V supervised)	VIT-	2.86	2.93	3.02	V	VDD = 2.7V to 6V, TA = -40°C to +85°C	3
Negative-going input threshold voltage, SENSE2 (1.8V supervised)	VIT-	1.64	1.68	1.73	V	VDD = 2.7V to 6V, TA = -40°C to +85°C	3
Low-level output voltage	VOL			0.2	V	VDD = 2.7V to 6V, IOL = 20µA	3
Low-level output voltage	VOL			0.4	V	VDD = 3.3V, IOL = 2mA	3
Power-up reset voltage				0.4	V	VDD ≥ 1.1V, IOL = 20µA	3
Hysteresis at VSENSEn input	Vhys		15		mV	VIT- = 1.68V	3
Hysteresis at VSENSEn input	Vhys		30		mV	VIT- = 2.93V	3
Average high-level input current, WDI	IH(AV)		100	150	µA	WDI = VDD = 6V, time average (dc = 88%)	3
Average low-level input current, WDI	IL(AV)		-15	-20	µA	WDI = 0V, VDD = 6V, time average (dc = 12%)	3
High-level input current, WDI	IIH		120	170	µA	WDI = VDD = 6V	3
High-level input current, MR	IIH		-130	-180	µA	MR = 0.7 × VDD, VDD = 6V	3
High-level input current, SENSE1	IIH		5	8	µA	VSENSE1 = VDD = 6V	3
High-level input current, SENSE2	IIH		6	9	µA	VSENSE2 = VDD = 6V	3
Low-level input current, WDI	IIL		-120	-170	µA	WDI = 0V, VDD = 6V	3
Low-level input current, MR	IIL		-430	-600	µA	MR = 0V, VDD = 6V	3
Low-level input current, SENSEn	IIL	-1		1	µA	VSENSE1,2 = 0V	3
Supply current	IDD			40	µA		3
Input capacitance	CI		10		pF	VI = 0V to VDD	3
Watchdog time-out	t(out)	1.1	1.6	2.3	s	VI(SENSEn) ≥ VIT+ +0.2V, MR ≥ 0.7 × VDD, see Timing Diagram	4
Delay time	td	140	200	280	ms	VI(SENSEn) ≥ VIT+ +0.2V, MR ≥ 0.7 × VDD, see Timing Diagram	4
Pulse width, SENSEn	tw	6			µs	VSENSEnL = VIT- -0.2V, VSENSEnH = VIT+ +0.2V	4
Pulse width, MR	tw	100			ns		4
Pulse width, WDI	tw	100			ns	VIH = 0.7 × VDD, VIL = 0.3 × VDD	4
Propagation delay time, MR to RESET, high-to-low level output	tPHL		200	500	ns	VI(SENSEn) ≥ VIT+ +0.2V, VIH = 0.7 × VDD, VIL = 0.3 × VDD	4
Propagation delay time, MR to RESET, low-to-high level output	tPLH		200	500	ns	VI(SENSEn) ≥ VIT+ +0.2V, VIH = 0.7 × VDD, VIL = 0.3 × VDD	4
Propagation delay time, SENSEn to RESET, high-to-low level output	tPHL		1	5	µs	VIH = VIT+ +0.2V, VIL = VIT- -0.2V, MR ≥ 0.7 × VDD	4
Propagation delay time, SENSEn to RESET, low-to-high level output	tPLH		1	5	µs	VIH = VIT+ +0.2V, VIL = VIT- -0.2V, MR ≥ 0.7 × VDD	4

CAD (KiCad official)

Symbol: TPS3305-18DGNR
Footprint: Package_SO:MSOP-8_3x3mm_P0.65mm
3D model: MSOP-8 (KiCad packages3D, STEP)
3D model files: tps3305-18dgnr-etched.step / tps3305-18dgnr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps3305-18dgnr.step / tps3305-18dgnr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (20 pp, sha256 2ae8290d9b80ba2a, retrieved 2026-11-05, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

TPS3305-18DGNR

Verified TPS3305-18DGNR

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

README