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74LVT126PW

Public Made by Adom

by adom

Nexperia Buffers, Drivers, Receivers, Transceivers, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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74LVT126PW

Nexperia · Buffers, Drivers, Receivers, Transceivers · TSSOP-14

74LVT126PW from Nexperia, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1OE input Output enable input for buffer 1; a LOW on nOE puts outputs 1Y into the high-impedance OFF-state.
2 1A input Data input for buffer 1, overvoltage tolerant to 5.5 V with bus-hold, operating from 0 V to 5.5 V.
3 1Y output 3-state data output of buffer 1, which goes high impedance when 1OE is LOW.
4 2OE input Output enable input for buffer 2; a LOW on nOE puts outputs 2Y into the high-impedance OFF-state.
5 2A input Data input for buffer 2, overvoltage tolerant to 5.5 V with bus-hold, operating from 0 V to 5.5 V.
6 2Y output 3-state data output of buffer 2, which goes high impedance when 2OE is LOW.
7 GND power_in Ground (0 V) reference for all voltages on the device.
8 3Y output 3-state data output of buffer 3, which goes high impedance when 3OE is LOW.
9 3A input Data input for buffer 3, overvoltage tolerant to 5.5 V with bus-hold, operating from 0 V to 5.5 V.
10 3OE input Output enable input for buffer 3; a LOW on nOE puts outputs 3Y into the high-impedance OFF-state.
11 4Y output 3-state data output of buffer 4, which goes high impedance when 4OE is LOW.
12 4A input Data input for buffer 4, overvoltage tolerant to 5.5 V with bus-hold, operating from 0 V to 5.5 V.
13 4OE input Output enable input for buffer 4; a LOW on nOE puts outputs 4Y into the high-impedance OFF-state.
14 VCC power_in Supply voltage, specified from 2.7 V to 3.6 V.

Key specifications

Parameter Value
Manufacturer Nexperia
Package TSSOP-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
supply voltage VCC -0.5 4.6 V 3
input voltage VI -0.5 7 V 3
output voltage VO -0.5 7 V output in OFF-state or HIGH-state 3
input clamping current IIK -50 mA VI < 0 V 3
output clamping current IOK -50 mA VO < 0 V 3
output current IO 128 mA output in LOW-state 3
output current IO -64 mA output in HIGH-state 3
storage temperature Tstg -65 150 °C 3
junction temperature Tj 150 °C 3
supply voltage VCC 2.7 3.6 V 4
input voltage VI 0 5.5 V 4
HIGH-level output current IOH -32 mA 4
LOW-level output current IOL 32 mA none 4
LOW-level output current IOL 64 mA current duty cycle ≤ 50 %; f ≥ 1 kHz 4
ambient temperature Tamb -40 85 °C in free air 4
input transition rise and fall rate Δt/ΔV 10 ns/V outputs enabled 4
input clamping voltage VIK -1.2 -0.9 V VCC = 2.7 V; IIK = -18 mA 4
HIGH-level input voltage VIH 2 V 4
LOW-level input voltage VIL 0.8 V 4
HIGH-level output voltage VOH 2.4 2.5 V VCC = 2.7 V; IOH = -8 mA 4
HIGH-level output voltage VOH 2 2.2 V VCC = 3.0 V; IOH = -32 mA 4
LOW-level output voltage VOL 0.1 0.2 V VCC = 2.7 V; IOL = 100 μA 4
LOW-level output voltage VOL 0.3 0.5 V VCC = 2.7 V; IOL = 24 mA 4
LOW-level output voltage VOL 0.25 0.4 V VCC = 3.0 V; IOL = 16 mA 4
LOW-level output voltage VOL 0.4 0.55 V VCC = 3.0 V; IOL = 64 mA 4
input leakage current, all input pins II 1 10 μA VCC = 0 V or 3.6 V; VI = 5.5 V 4
input leakage current, control pins II -1 1 μA VCC = 3.6 V; VI = VCC or GND 4
input leakage current, data pins II 0.1 1 μA VCC = 3.6 V; VI = VCC 4
input leakage current, data pins II -1 -5 μA VCC = 3.6 V; VI = 0 V 4
power-off leakage current IOFF -100 1 100 μA VCC = 0 V; VI or VO = 0 V to 4.5 V 4
bus hold LOW current IBHL 75 150 μA VCC = 3 V; VI = 0.8 V 4
bus hold HIGH current IBHH -75 -150 μA VCC = 3 V; VI = 2.0 V 4
bus hold LOW overdrive current IBHLO 500 μA VCC = 3.6 V; VI = 0 V to 3.6 V 4
bus hold HIGH overdrive current IBHHO -500 μA VCC = 3.6 V; VI = 0 V to 3.6 V 4
external current output in HIGH-state IEX 60 125 μA when VO > VCC; VO = 5.5 V; VCC = 3.0 V 4
power-up/power-down output current IO(pu/pd) -100 100 μA VCC ≤ 1.2 V; VO = 0.5 V to VCC; VI = GND or VCC; nOE = don't care 4
OFF-state output current, output HIGH IOZ 1 5 μA VCC = 3.6 V; output HIGH: VO = 3.0 V 5
OFF-state output current, output LOW IOZ -1 -5 μA VCC = 3.6 V; output LOW: VO = 0.5 V 5
supply current, outputs HIGH ICC 0.13 0.19 mA VCC = 3.6 V; VI = GND or VCC; IO = 0 A; outputs HIGH 5
supply current, outputs LOW ICC 2 7 mA VCC = 3.6 V; VI = GND or VCC; IO = 0 A; outputs LOW 5
supply current, outputs disabled ICC 0.13 0.19 mA VCC = 3.6 V; VI = GND or VCC; IO = 0 A; outputs disabled 5
additional supply current per input pin ΔICC 0.1 0.2 mA per input pin; VCC = 3 V to 3.6 V; one input at VCC - 0.6 V and other inputs at VCC or GND 5
input capacitance CI 4 pF VI = 0 V or VCC 5
output capacitance CO 8 pF outputs disabled; VO = 0 V or 3.0 V 5
LOW to HIGH propagation delay tPLH 4.5 ns VCC = 2.7 V; nA to nY; see Fig. 6 5
LOW to HIGH propagation delay tPLH 1 2.3 3.8 ns VCC = 3.3 V ± 0.3 V; nA to nY; see Fig. 6 5
HIGH to LOW propagation delay tPHL 4.4 ns VCC = 2.7 V; nA to nY; see Fig. 6 5
HIGH to LOW propagation delay tPHL 1 2.4 3.9 ns VCC = 3.3 V ± 0.3 V; nA to nY; see Fig. 6 5
OFF-state to HIGH propagation delay tPZH 6.1 ns VCC = 2.7 V; nOE to nY; see Fig. 7 5
OFF-state to HIGH propagation delay tPZH 1 3.6 5.4 ns VCC = 3.3 V ± 0.3 V; nOE to nY; see Fig. 7 5
OFF-state to LOW propagation delay tPZL 5.8 ns VCC = 2.7 V; nOE to nY; see Fig. 7 5
OFF-state to LOW propagation delay tPZL 1.1 3.6 5.2 ns VCC = 3.3 V ± 0.3 V; nOE to nY; see Fig. 7 5
HIGH to OFF-state propagation delay tPHZ 4.3 ns VCC = 2.7 V; nOE to nY; see Fig. 7 5
HIGH to OFF-state propagation delay tPHZ 1 2.2 3.8 ns VCC = 3.3 V ± 0.3 V; nOE to nY; see Fig. 7 5
LOW to OFF-state propagation delay tPLZ 6.1 ns VCC = 2.7 V; nOE to nY; see Fig. 7 5
LOW to OFF-state propagation delay tPLZ 1.3 3.6 5.5 ns VCC = 3.3 V ± 0.3 V; nOE to nY; see Fig. 7 5

CAD (KiCad official)

  • Symbol: 74LVT126PW
  • Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
  • 3D model: TSSOP-14 (KiCad packages3D, STEP)
  • 3D model files: 74lvt126pw-etched.step / 74lvt126pw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74lvt126pw.step / 74lvt126pw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (13 pp, sha256 b83a8b570c8da964, retrieved 2026-10-18, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus off (skipped (clean text read)), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF