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AT25SF128A-SHB-T

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Dialog Semiconductor Adesto Adesto Technologies NOR FLASH, SOP-8-208mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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AT25SF128A-SHB-T

Dialog Semiconductor Adesto Adesto Technologies · NOR FLASH · SOP-8-208mil

AT25SF128A-SHB-T from Dialog Semiconductor Adesto Adesto Technologies, in a SOP-8-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CS input Chip select: when high the device is deselected, inputs are ignored and outputs are high impedance; a falling edge is required after power-up before any command, and a 10k pull-up from CS to VCC is recommended.
2 SO (IO1) bidirectional Serial data output for single-bit commands, shifted out on the falling edge of SCK; becomes IO1 for dual and quad commands.
3 WP (IO2) bidirectional Write protect for single-bit and dual commands (driven low to protect the status registers when QE=0 and SRP1:SRP0=01); becomes IO2 in quad mode, has an internal pull-up and may be left unconnected if unused.
4 GND power_in Ground reference for the VCC supply voltage.
5 SI (IO0) bidirectional Serial data input for single-bit commands, latched on the rising edge of SCK; becomes IO0 for dual and quad commands.
6 SCK input Serial clock providing the synchronization reference; commands, addresses and data are latched on the rising edge and data output changes after the falling edge.
7 HOLD (IO3) bidirectional Pauses a serial transfer without resetting the clock sequence when CS is low and HOLD is driven low with SCK low; internally pulled high, and becomes IO3 in quad-I/O mode.
8 VCC power_in Core and I/O power supply, single supply of 2.7 V to 3.6 V for all read, program and erase functions.

Key specifications

Parameter Value
Manufacturer Dialog Semiconductor Adesto Adesto Technologies
Package SOP-8-208mil
Category Memory
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input Leakage Current ILI -2 2 μA 49
Output Leakage Current ILO -2 2 μA 49
Standby Current ICC1 13 25 μA CS = VCC, VIN = VCC or GND 49
Deep Power-Down Current ICC2 2 5 μA CS = VCC, VIN = VCC or GND 49
Operating Current (Read) at 120 MHz ICC3 12 18 mA SCK = 0.1VCC/0.9VCC, at 120 MHz, Q = Open (1,,2*4 I/O) 49
Operating Current (Read) at 80 MHz ICC3 10 16 mA SCK = 0.1VCC/0.9VCC, at 80MHz, Q = Open (1,,2*4 I/O) 49
Operating Current (Page Program) ICC4 15 20 mA CS = VCC 49
Operating Current (WRSR) ICC5 5 mA CS = VCC 49
Operating Current (Sector Erase) ICC6 9 20 mA CS = VCC 49
Operating Current (Block Erase) ICC7 9 20 mA CS = VCC 49
Operating Current (Chip Erase) ICC8 9 20 mA CS = VCC 49
Input Low Voltage VIL -0.5 0.2 V max printed as 0.2VCC (max unit xVCC) 49
Input High Voltage VIH 0.8 0.4 V min printed as 0.8 VCC (unit xVCC); max printed as VCC+0.4 V (unit V from VCC) 49
Output Low Voltage VOL 0.4 V IOL = 100 μA 49
Output High Voltage VOH -0.2 V from VCC IOH = -100 μA; printed as VCC-0.2 V 49
Input Voltage on I/O pins (latch-up) -1 1 V Printed -1.0 V to VCC + 1.0 V; max unit V from VCC 47
VCC Current (latch-up) -100 100 mA 47
Erase/Program Cycles (endurance) 100000 Cycles 4 kbytes sector, 32/64 kbytes block, or full chip; 85 °C 47
Data Retention 20 Years 85 °C; full temperature range 47
Supply Voltage (absolute max) VCC -0.5 4 V 47
Voltage Applied to Any Pin VIO -0.5 4 V Relative to Ground 47
Transient Voltage on any Pin VIOT -2 2 V <20 ns transient relative to ground; printed -2.0 to VCC + 2.0 V (max unit V from VCC) 47
Storage Temperature TSTG -65 150 °C 47
Electrostatic Discharge Voltage VESD -2000 2000 V Human Body Model (JESD22-A114) 47
Supply Voltage (operating) VCC 2.7 3.6 V 47
Operating Temperature (Industrial) TA -40 85 °C Industrial 47
Power-up time VCC(min) to CS low tVSL 300 μs VCC (min) to CS low 48
Clock frequency for Quad Output Fast Read (6Bh) Fc1 133 MHz 3.0 V-3.6 V supply; min printed as DC 51
Clock frequency for Read Data (03h) Fc2 70 MHz 2.7 V-3.6 V supply; min printed as DC 51
Clock frequency except 6Bh or 03h Fc3 120 MHz 3.0 V-3.6 V supply; min printed as DC 51
Clock frequency except 03h Fc4 108 MHz 2.7 V-3.6 V supply; min printed as DC 51
Serial Clock High Time tCLH 3.75 ns 51
Serial Clock Low Time tCLL 3.75 ns 51
Serial Clock Rise Time (Slew Rate) tCLCH 0.1 V/ns Footnote 1: tested with clock frequency lower than 50 MHz 51
Serial Clock Fall Time (Slew Rate) tCHCL 0.1 V/ns Footnote 1: tested with clock frequency lower than 50 MHz 51
CS Active Setup Time tSLCH 5 ns 51
CS Active Hold Time tCHSH 5 ns 51
CS Not Active Setup Time tSHCH 5 ns 51
CS Not Active Hold Time tCHSL 5 ns 51
CS High Time (read/write) tSHSL 20 ns 51
Output Disable Time tSHQZ 6 ns 51
Output Hold Time tCLQX 0 ns 51
Data In Setup Time tDVCH 2 ns 51
Data In Hold Time tCHDX 2 ns 51
Clock Low To Output Valid tCLQV 7 ns 51
Write Protect Setup Time Before CS Low tWHSL 20 ns 52
Write Protect Hold Time After CS High tSHWL 100 ns 52
CS High To Deep Power-Down Mode tDP 20 µs 52
CS High To Standby Mode Without Electronic Signature Read tRES1 20 µs 52
CS High To Standby Mode With Electronic Signature Read tRES2 20 µs 52
CS High To Next Command After Suspend tSUS 20 µs 52
Write Status Register Cycle Time tW 5 30 ms 52
Byte Program Time (First Byte) tBP1 30 50 µs Footnote 2: for multiple bytes tBPn = tBP1 + tBP2 * N 52
Additional Byte Program Time (After First Byte) tBP2 2.5 12 µs Footnote 2 52
Page Programming Time tPP 0.6 2.4 ms 52
Sector Erase Time tSE 70 300 ms 52
Block Erase Time (32K Bytes) tBE 0.15 1.6 sec 32K byte block 52
Block Erase Time (64K Bytes) tBE 0.25 2 sec 64K byte block 52
Chip Erase Time tCE 30 120 sec 52

CAD (KiCad official)

  • Symbol: AT25SF128A-SHB-T
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8-208mil (KiCad packages3D, STEP)
  • 3D model files: at25sf128a-shb-t-etched.step / at25sf128a-shb-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); at25sf128a-shb-t.step / at25sf128a-shb-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Dialog Semiconductor Adesto Adesto Technologies datasheet (59 pp, sha256 ecd2107ed907b0a2, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF