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SN74ALS21ADR
Public Made by Adomby adom
Texas Instruments Logic Gates, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSN74ALS21ADR
Texas Instruments · Logic Gates · SOIC-14
SN74ALS21ADR from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Data input A of gate 1 in the 4-input positive-AND function Y = A·B·C·D; a low level forces Y low, with VIH min 2 V and VIL max 0.8 V. |
| 2 | 1B | input | Data input B of gate 1 in the 4-input positive-AND function Y = A·B·C·D; a low level forces Y low, with VIH min 2 V and VIL max 0.8 V. |
| 3 | NC | unconnected | No internal connection. |
| 4 | 1C | input | Data input C of gate 1 in the 4-input positive-AND function Y = A·B·C·D; a low level forces Y low, with VIH min 2 V and VIL max 0.8 V. |
| 5 | 1D | input | Data input D of gate 1 in the 4-input positive-AND function Y = A·B·C·D; a low level forces Y low, with VIH min 2 V and VIL max 0.8 V. |
| 6 | 1Y | output | Output of gate 1 (Y = A·B·C·D); for the SN74ALS21A it is rated IOH −0.4 mA high-level and IOL 8 mA low-level. |
| 7 | GND | power_in | Ground reference for the device. |
| 8 | 2Y | output | Output of gate 2 (Y = A·B·C·D); for the SN74ALS21A it is rated IOH −0.4 mA high-level and IOL 8 mA low-level. |
| 9 | 2A | input | Data input A of gate 2 in the 4-input positive-AND function Y = A·B·C·D; a low level forces Y low, with VIH min 2 V and VIL max 0.8 V. |
| 10 | 2B | input | Data input B of gate 2 in the 4-input positive-AND function Y = A·B·C·D; a low level forces Y low, with VIH min 2 V and VIL max 0.8 V. |
| 11 | NC | unconnected | No internal connection. |
| 12 | 2C | input | Data input C of gate 2 in the 4-input positive-AND function Y = A·B·C·D; a low level forces Y low, with VIH min 2 V and VIL max 0.8 V. |
| 13 | 2D | input | Data input D of gate 2 in the 4-input positive-AND function Y = A·B·C·D; a low level forces Y low, with VIH min 2 V and VIL max 0.8 V. |
| 14 | VCC | power_in | Supply voltage, 4.5 V to 5.5 V (5 V nominal) per the recommended operating conditions. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-14 |
| Category | Logic |
| Pins | 14 |
CAD (KiCad official)
- Symbol:
SN74ALS21ADR - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files:
sn74als21adr-etched.step/sn74als21adr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74als21adr.step/sn74als21adr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (19 pp, sha256
cd5010938814bd38, retrieved 2026-10-11, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).