A3P030-1QNG48 from Microsemi, in a QFN-48(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	IO82RSB1	bidirectional	User I/O in bank 1 (IO82RSB1).
2	GEC0/IO73RSB1	bidirectional	User I/O in bank 1 that doubles as global GEC0 with access to the global network.
3	GEA0/IO72RSB1	bidirectional	User I/O in bank 1 that doubles as global GEA0 with access to the global network.
4	GEB0/IO71RSB1	bidirectional	User I/O in bank 1 that doubles as global GEB0 with access to the global network.
5	GND	power_in	Ground supply voltage to the core, I/O outputs, and I/O logic.
6	VCCIB1	power_in	Supply voltage to bank 1 I/O output buffers and I/O logic; 1.5 V, 1.8 V, 2.5 V, or 3.3 V nominal.
7	IO68RSB1	bidirectional	User I/O in bank 1 (IO68RSB1).
8	IO67RSB1	bidirectional	User I/O in bank 1 (IO67RSB1).
9	IO66RSB1	bidirectional	User I/O in bank 1 (IO66RSB1).
10	IO65RSB1	bidirectional	User I/O in bank 1 (IO65RSB1).
11	IO64RSB1	bidirectional	User I/O in bank 1 (IO64RSB1).
12	IO62RSB1	bidirectional	User I/O in bank 1 (IO62RSB1).
13	IO61RSB1	bidirectional	User I/O in bank 1 (IO61RSB1).
14	IO60RSB1	bidirectional	User I/O in bank 1 (IO60RSB1).
15	IO57RSB1	bidirectional	User I/O in bank 1 (IO57RSB1).
16	IO55RSB1	bidirectional	User I/O in bank 1 (IO55RSB1).
17	IO53RSB1	bidirectional	User I/O in bank 1 (IO53RSB1).
18	VCC	power_in	Core supply voltage, nominally 1.5 V; also required to power the JTAG state machine.
19	VCCIB1	power_in	Supply voltage to bank 1 I/O output buffers and I/O logic; 1.5 V, 1.8 V, 2.5 V, or 3.3 V nominal.
20	IO46RSB1	bidirectional	User I/O in bank 1 (IO46RSB1).
21	IO42RSB1	bidirectional	User I/O in bank 1 (IO42RSB1).
22	TCK	input	JTAG test clock input for boundary scan, ISP, and UJTAG, with no internal pull resistor; tie to GND through 200 ohm to 1 kohm (500 ohm to 1 kohm at 1.5/1.8 V VJTAG) if JTAG is unused.
23	TDI	input	JTAG test data serial input with an internal weak pull-up resistor.
24	TMS	input	JTAG test mode select controlling the boundary scan pins, with an internal weak pull-up resistor.
25	VPUMP	power_in	Programming supply, 3.3 V nominal for programming; may float or be tied to any voltage up to the VPUMP maximum in normal operation, and tying it to ground shuts off the charge pump.
26	TDO	output	JTAG test data serial output for boundary scan, ISP, and UJTAG.
27	TRST	input	Active-low asynchronous JTAG boundary scan reset input with an internal weak pull-up resistor; tie to GND via resistor if JTAG is unused.
28	VJTAG	power_in	JTAG supply voltage for the dedicated JTAG bank, 1.5 V to 3.3 V nominal; VCC must also be powered for JTAG operation.
29	IO38RSB0	bidirectional	User I/O in bank 0 (IO38RSB0).
30	GDB0/IO34RSB0	bidirectional	User I/O in bank 0 that doubles as global GDB0 with access to the global network.
31	GDA0/IO33RSB0	bidirectional	User I/O in bank 0 that doubles as global GDA0 with access to the global network.
32	GDC0/IO32RSB0	bidirectional	User I/O in bank 0 that doubles as global GDC0 with access to the global network.
33	VCCIB0	power_in	Supply voltage to bank 0 I/O output buffers and I/O logic; 1.5 V, 1.8 V, 2.5 V, or 3.3 V nominal.
34	GND	power_in	Ground supply voltage to the core, I/O outputs, and I/O logic.
35	VCC	power_in	Core supply voltage, nominally 1.5 V; also required to power the JTAG state machine.
36	IO25RSB0	bidirectional	User I/O in bank 0 (IO25RSB0).
37	IO24RSB0	bidirectional	User I/O in bank 0 (IO24RSB0).
38	IO22RSB0	bidirectional	User I/O in bank 0 (IO22RSB0).
39	IO20RSB0	bidirectional	User I/O in bank 0 (IO20RSB0).
40	IO18RSB0	bidirectional	User I/O in bank 0 (IO18RSB0).
41	IO16RSB0	bidirectional	User I/O in bank 0 (IO16RSB0).
42	IO14RSB0	bidirectional	User I/O in bank 0 (IO14RSB0).
43	IO10RSB0	bidirectional	User I/O in bank 0 (IO10RSB0).
44	IO08RSB0	bidirectional	User I/O in bank 0 (IO08RSB0).
45	IO06RSB0	bidirectional	User I/O in bank 0 (IO06RSB0).
46	IO04RSB0	bidirectional	User I/O in bank 0 (IO04RSB0).
47	IO02RSB0	bidirectional	User I/O in bank 0 (IO02RSB0).
48	IO00RSB0	bidirectional	User I/O in bank 0 (IO00RSB0).
49	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Microsemi
Package	QFN-48(6x6)
Category	Single Chip Microcomputer/Microcontroller
Pins	49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
DC core supply voltage	VCC	-0.3		1.65	V		14
JTAG DC voltage	VJTAG	-0.3		3.75	V		14
Programming voltage	VPUMP	-0.3		3.75	V		14
DC I/O output buffer supply voltage	VCCI	-0.3		3.75	V		14
DC I/O input buffer supply voltage	VMV	-0.3		3.75	V		14
Storage temperature	TSTG	-65		150	°C		14
Junction temperature	TJ			125	°C		14
Junction temperature (commercial)	TJ	0		85	°C	Commercial	15
1.5 V DC core supply voltage	VCC	1.425		1.575	V	Commercial	15
JTAG DC voltage	VJTAG	1.4		3.6	V		15
Programming voltage, programming mode	VPUMP	3.15		3.45	V	Programming Mode	15
Programming voltage, operation	VPUMP	0		3.6	V	Operation	15
I/O supply 1.5 V	VCCI/VMV	1.425		1.575	V	1.5 V DC supply	15
I/O supply 1.8 V	VCCI/VMV	1.7		1.9	V	1.8 V DC supply	15
I/O supply 2.5 V	VCCI/VMV	2.3		2.7	V	2.5 V DC supply	15
I/O supply 3.3 V	VCCI/VMV	3		3.6	V	3.3 V DC supply	15
I/O supply 3.3 V wide range	VCCI/VMV	2.7		3.6	V	3.3 V wide range	15
Quiescent supply current (typical)	IDD		2		mA	Typical (25°C)	20
Quiescent supply current (commercial max)	IDD			10	mA	Max. (Commercial)	20
Input capacitance	CIN			8	pF	VIN = 0, f = 1.0 MHz	39
Input capacitance on clock pin	CINCLK			8	pF	VIN = 0, f = 1.0 MHz	39
Input leakage current IIL (commercial)	IIL			10	µA	3.3 V LVTTL/LVCMOS, commercial	34
Input leakage current IIH (commercial)	IIH			10	µA	3.3 V LVTTL/LVCMOS, commercial	34
Low-level input voltage 3.3 V LVTTL	VIL	-0.3		0.8	V	3.3 V LVTTL/LVCMOS	46
High-level input voltage 3.3 V LVTTL	VIH	2		3.6	V	3.3 V LVTTL/LVCMOS	46
Low-level output voltage 3.3 V LVTTL	VOL			0.4	V	3.3 V LVTTL/LVCMOS	46
High-level output voltage 3.3 V LVTTL	VOH	2.4			V	3.3 V LVTTL/LVCMOS	46
Weak pull-up resistance 3.3 V	R(WEAK PULL-UP)	10		45	kΩ	VCCI = 3.3 V	41
Weak pull-down resistance 3.3 V	R(WEAK PULL-DOWN)	10		45	kΩ	VCCI = 3.3 V	41
Junction-to-case thermal resistance (QFN, A3P030, 132 pin)	θjc		0.4		°C/W	QN132 A3P030; not QN48	19
Junction-to-ambient thermal resistance still air (QFN, A3P030, 132 pin)	θja		21.4		°C/W	Still air; QN132 A3P030; not QN48	19

CAD (KiCad official)

Symbol: A3P030-1QNG48
Footprint: Package_DFN_QFN:QFN-48-1EP_6x6mm_P0.4mm_EP4.2x4.2mm
3D model: QFN-48(6x6), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
3D model files: a3p030-1qng48-etched.step / a3p030-1qng48-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); a3p030-1qng48.step / a3p030-1qng48.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Microsemi datasheet (221 pp, sha256 2a08c1e8322ee15d, retrieved 2026-10-31, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

A3P030-1QNG48

Verified A3P030-1QNG48

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

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