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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

TM4C123GH6PMI7R

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)

TM4C123GH6PMI7R from Texas Instruments, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	PB6	bidirectional	GPIO port B bit 6 (TTL), also Module 0 PWM 0 output, SSI2 receive, and 16/32-bit Timer 0 CCP0, selected via AFSEL and PMCn.
2	VDDA	power_in	Positive supply for the analog circuits (ADC, analog comparators), which must meet the voltage specification in Table 24-5 regardless of system implementation.
3	GNDA	power_in	Ground reference for the analog circuits (ADC, analog comparators), separated from GND to limit digital noise.
4	PB7	bidirectional	GPIO port B bit 7 (TTL), also Module 0 PWM 1 output, SSI2 transmit, and 16/32-bit Timer 0 CCP1.
5	PF4	bidirectional	GPIO port F bit 4 (TTL), also QEI0 index, Module 1 PWM fault 0 input, Timer 2 CCP0, and USB0 EPEN output (optional host-mode power enable).
6	PE3	bidirectional	GPIO port E bit 3, also ADC analog input 0 (AIN0); analog inputs are not 5-V tolerant and pass through an isolation circuit.
7	PE2	bidirectional	GPIO port E bit 2, also ADC analog input 1 (AIN1); analog inputs are not 5-V tolerant and pass through an isolation circuit.
8	PE1	bidirectional	GPIO port E bit 1, also ADC analog input 2 (AIN2) and UART7 transmit; analog inputs are not 5-V tolerant.
9	PE0	bidirectional	GPIO port E bit 0, also ADC analog input 3 (AIN3) and UART7 receive; analog inputs are not 5-V tolerant.
10	PD7	bidirectional	GPIO port D bit 7 (TTL), also the NMI input, QEI0 phase B, UART2 transmit, and Wide Timer 5 CCP1; it is locked and must be unlocked and committed through GPIOLOCK/GPIOCR to be reprogrammed.
11	VDD	power_in	Positive supply for I/O and some logic.
12	GND	power_in	Ground reference for logic and I/O pins.
13	PC7	bidirectional	GPIO port C bit 7 (TTL), also analog comparator 0 negative input (C0-), UART3 transmit, USB0 PFLT input, and Wide Timer 1 CCP1.
14	PC6	bidirectional	GPIO port C bit 6 (TTL), also analog comparator 0 positive input (C0+), QEI1 phase B, UART3 receive, USB0 EPEN output, and Wide Timer 1 CCP0.
15	PC5	bidirectional	GPIO port C bit 5 (TTL), also analog comparator 1 positive input (C1+), PWM0 output 7, QEI1 phase A, UART1 CTS/TX, UART4 transmit, and Wide Timer 0 CCP1.
16	PC4	bidirectional	GPIO port C bit 4 (TTL), also analog comparator 1 negative input (C1-), QEI1 index, PWM0 output 6, UART1 RTS/RX, UART4 receive, and Wide Timer 0 CCP0.
17	PA0	bidirectional	GPIO port A bit 0 (TTL), also CAN1 receive and UART0 receive (default UART function after reset).
18	PA1	bidirectional	GPIO port A bit 1 (TTL), also CAN1 transmit and UART0 transmit (default UART function after reset).
19	PA2	bidirectional	GPIO port A bit 2 (TTL), also SSI0 clock (default SSI function after reset).
20	PA3	bidirectional	GPIO port A bit 3 (TTL), also SSI0 frame signal (default SSI function after reset).
21	PA4	bidirectional	GPIO port A bit 4 (TTL), also SSI0 receive (default SSI function after reset).
22	PA5	bidirectional	GPIO port A bit 5 (TTL), also SSI0 transmit (default SSI function after reset).
23	PA6	bidirectional	GPIO port A bit 6, also I2C1 clock (open-drain with active pull-up; the port pin must not be configured as open drain), and PWM1 output 2.
24	PA7	bidirectional	GPIO port A bit 7, also I2C1 data (open-drain; should be set open drain via GPIOODR), and PWM1 output 3.
25	VDDC	power_out	Positive 1.2 V logic supply generated by the on-chip LDO; connect only to the other VDDC pins and the external capacitor specified in Table 24-12.
26	VDD	power_in	Positive supply for I/O and some logic.
27	GND	power_in	Ground reference for logic and I/O pins.
28	PF0	bidirectional	GPIO port F bit 0 (TTL), also analog comparator 0 output, CAN0 receive, PWM1 output 4, NMI, QEI0 phase A, SSI1 receive, Timer 0 CCP0, and UART1 RTS; it is locked and requires GPIOLOCK/GPIOCR unlock to reprogram.
29	PF1	bidirectional	GPIO port F bit 1 (TTL), also analog comparator 1 output, PWM1 output 5, QEI0 phase B, SSI1 transmit, Timer 0 CCP1, Trace data 1, and UART1 CTS.
30	PF2	bidirectional	GPIO port F bit 2 (TTL), also PWM0 fault 0 input, PWM1 output 6, SSI1 clock, Timer 1 CCP0, and Trace data 0.
31	PF3	bidirectional	GPIO port F bit 3 (TTL), also CAN0 transmit, PWM1 output 7, SSI1 frame signal, Timer 1 CCP1, and Trace clock.
32	WAKE	input	External input (TTL) that brings the processor out of Hibernate mode when asserted.
33	HIB	output	TTL output that indicates the processor is in Hibernate mode.
34	XOSC0	input	Hibernation module oscillator crystal input or external clock reference input for a 32.768-kHz crystal or oscillator.
35	GNDX	power_in	Ground for the Hibernation oscillator; connect to digital ground with the crystal load capacitors (crystal) or directly to digital ground (external oscillator).
36	XOSC1	output	Hibernation oscillator crystal output; leave unconnected when using a single-ended clock source.
37	VBAT	power_in	Power source for the Hibernation module, normally connected to the positive terminal of a battery as battery backup supply.
38	RST	input	TTL system reset input.
39	GND	power_in	Ground reference for logic and I/O pins.
40	OSC0	input	Main oscillator crystal input or external clock reference input (analog).
41	OSC1	output	Main oscillator crystal output; leave unconnected when using a single-ended clock source.
42	VDD	power_in	Positive supply for I/O and some logic.
43	PD4	bidirectional	GPIO port D bit 4, not 5-V tolerant; also UART6 receive, USB0 D- differential data pin (analog), and Wide Timer 4 CCP0.
44	PD5	bidirectional	GPIO port D bit 5, not 5-V tolerant; also UART6 transmit, USB0 D+ differential data pin (analog), and Wide Timer 4 CCP1.
45	PB0	bidirectional	GPIO port B bit 0, not 5-V tolerant; also Timer 2 CCP0, UART1 receive, and USB0 ID sense input (analog).
46	PB1	bidirectional	GPIO port B bit 1, not 5-V tolerant; also Timer 2 CCP1, UART1 transmit, and USB0 VBUS analog input/output used in session request protocol.
47	PB2	bidirectional	GPIO port B bit 2, also I2C0 clock (open-drain with active pull-up; must not be configured as open drain) and Timer 3 CCP0.
48	PB3	bidirectional	GPIO port B bit 3, also I2C0 data (open-drain) and Timer 3 CCP1.
49	PC3	bidirectional	GPIO port C bit 3 (TTL), also JTAG TDO and SWO output and Timer 5 CCP1.
50	PC2	bidirectional	GPIO port C bit 2 (TTL), also JTAG TDI input and Timer 5 CCP0.
51	PC1	bidirectional	GPIO port C bit 1 (TTL), also JTAG TMS / SWDIO and Timer 4 CCP1.
52	PC0	bidirectional	GPIO port C bit 0 (TTL), also JTAG/SWD clock (TCK/SWCLK) and Timer 4 CCP0.
53	PD6	bidirectional	GPIO port D bit 6 (TTL), also PWM0 fault 0 input, QEI0 phase A, UART2 receive, and Wide Timer 5 CCP0.
54	VDD	power_in	Positive supply for I/O and some logic.
55	GND	power_in	Ground reference for logic and I/O pins.
56	VDDC	power_out	Positive 1.2 V logic supply generated by the on-chip LDO; connect only to the other VDDC pins and the external capacitor specified in Table 24-12.
57	PB5	bidirectional	GPIO port B bit 5 (TTL), also ADC analog input 11 (AIN11), CAN0 transmit, PWM0 output 3, SSI2 frame signal, and Timer 1 CCP1.
58	PB4	bidirectional	GPIO port B bit 4 (TTL), also ADC analog input 10 (AIN10), CAN0 receive, PWM0 output 2, SSI2 clock, and Timer 1 CCP0.
59	PE4	bidirectional	GPIO port E bit 4 (TTL), also ADC analog input 9 (AIN9), CAN0 receive, I2C2 clock (open-drain with active pull-up), PWM0 output 4, PWM1 output 2, and UART5 receive.
60	PE5	bidirectional	GPIO port E bit 5 (TTL), also ADC analog input 8 (AIN8), CAN0 transmit, I2C2 data (open-drain), PWM0 output 5, PWM1 output 3, and UART5 transmit.
61	PD0	bidirectional	GPIO port D bit 0 (TTL), also ADC analog input 7 (AIN7), I2C3 clock (open-drain with active pull-up), PWM0 output 6, PWM1 output 0, SSI1 and SSI3 clock, and Wide Timer 2 CCP0.
62	PD1	bidirectional	GPIO port D bit 1 (TTL), also ADC analog input 6 (AIN6), I2C3 data (open-drain), PWM0 output 7, PWM1 output 1, SSI1 and SSI3 frame signal, and Wide Timer 2 CCP1.
63	PD2	bidirectional	GPIO port D bit 2 (TTL), also ADC analog input 5 (AIN5), PWM0 fault 0 input, SSI1 and SSI3 receive, USB0 EPEN output, and Wide Timer 3 CCP0.
64	PD3	bidirectional	GPIO port D bit 3 (TTL), also ADC analog input 4 (AIN4), QEI0 index, SSI1 and SSI3 transmit, USB0 PFLT input, and Wide Timer 3 CCP1.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	LQFP-64(10x10)
Category	Embedded Processors & Controllers
Pins	64

CAD (KiCad official)

Symbol: TM4C123GH6PMI7R
Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
3D model files: tm4c123gh6pmi7r-etched.step / tm4c123gh6pmi7r-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tm4c123gh6pmi7r.step / tm4c123gh6pmi7r.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (1411 pp, sha256 108350fb9d6cabfc, retrieved 2026-10-11, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF