component
PY32F003F16U6TR
Public Made by Adomby adom
PUYA Microcontrollers (MCU/MPU/SOC), QFN-20-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownPY32F003F16U6TR
PUYA · Microcontrollers (MCU/MPU/SOC) · QFN-20-EP(3x3)
PY32F003F16U6TR from PUYA, in a QFN-20-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PA5 | bidirectional | COM-type GPIO (normal 5 V port with analog input/output); alternate functions include SPI1_SCK, ADC_IN5, LPTIM_ETR, TIM3_CH2, USART2_RX, MCO and EVENTOUT. |
| 2 | PA6 | bidirectional | COM-type GPIO (normal 5 V port with analog input/output); alternate functions include SPI1_MISO, ADC_IN6, TIM3_CH1, TIM1_BKIN, TIM16_CH1, LPUART_CTS, COMP1_OUT, USART1_CK, RTC_OUT and EVENTOUT. |
| 3 | PA7 | bidirectional | COM-type GPIO (normal 5 V port with analog input/output); alternate functions include SPI1_MOSI, ADC_IN7, TIM3_CH2, TIM1_CH1N, TIM14_CH1, TIM17_CH1, COMP2_OUT, USART1_TX, USART2_TX and I2C_SDA. |
| 4 | VSS | power_in | Ground pin (type G) for the device; VCC and VSS must always be connected to a supply within the allowed range. |
| 5 | PA12 | bidirectional | GPIO PA12 as printed in the QFN20 pinout figure; the extracted pages give no port structure, alternate-function or electrical limits for this pin. |
| 6 | VCC | power_in | Digital power supply; standard operating voltage is 1.7 V to 5.5 V (Table 6-4) and the absolute maximum VCC is -0.3 V to 6.25 V (Table 6-1). |
| 7 | PA13 | bidirectional | GPIO PA13 as printed in the QFN20 pinout figure; the extracted pages give no alternate-function or electrical limits for this pin. |
| 8 | PA14 | bidirectional | GPIO PA14 as printed in the QFN20 pinout figure; the extracted pages give no alternate-function or electrical limits for this pin. |
| 9 | PB5 | bidirectional | GPIO PB5 as printed in the QFN20 pinout figure; the extracted pages give no alternate-function or electrical limits for this pin. |
| 10 | PB6 | bidirectional | GPIO PB6 as printed in the QFN20 pinout figure; the extracted pages give no alternate-function or electrical limits for this pin. |
| 11 | PB7 | bidirectional | GPIO PB7; the programmable voltage detector (PVD) can monitor the voltage on PB7 as an alternative to VCC (section 3.5.2.3). |
| 12 | PF4-BOOT0 | bidirectional | GPIO PF4 shared with the BOOT0 boot-mode pin as printed in the QFN20 pinout figure; the boot selection behaviour is in section 3.3, which is not in the extracted pages. |
| 13 | PF0-OSC_IN | bidirectional | COM-type GPIO PF0 (normal 5 V port with analog input/output); also used as the OSC_IN input for the 4-32 MHz external crystal/resonator (HSE), with alternates USART2_RX, TIM14_CH1, USART1_RX, USART2_TX and I2C_SDA. |
| 14 | PF1-OSC_OUT | bidirectional | COM-type GPIO PF1 (normal 5 V port with analog input/output); also used as the OSC_OUT output for the 4-32 MHz external crystal/resonator (HSE), with alternates USART2_TX, USART1_TX, USART2_RX, I2C_SCL, SPI1_NSS and TIM14_CH1. |
| 15 | PF2-NRST | bidirectional | Reset-type port (RST, not usable for analog I/O) with NRST function and internal weak pull-up of 30 to 70 kΩ (typical 50 kΩ) per Table 6-20; alternates are MCO and USART2_RX. |
| 16 | PA0 | bidirectional | COM-type GPIO (normal 5 V port with analog input/output); alternate functions include USART1_CTS, ADC_IN0, COMP1_INM, USART2_CTS, COMP1_OUT, TIM1_CH3, TIM1_CH1N, SPI1_MISO, USART2_TX and IR_OUT. |
| 17 | PA1 | bidirectional | COM-type GPIO (normal 5 V port with analog input/output); alternate functions include SPI1_SCK, COMP1_INP, ADC_IN1, USART1_RTS, USART2_RTS, EVENTOUT, SPI1_MOSI, USART2_RX, TIM1_CH4, TIM1_CH2N and MCO. |
| 18 | PA2 | bidirectional | COM-type GPIO (normal 5 V port with analog input/output); alternate functions include SPI1_MOSI, COMP2_INM, ADC_IN2, USART1_TX, USART2_TX, LPUART_TX and COMP2_OUT. |
| 19 | PA3 | bidirectional | COM-type GPIO (normal 5 V port with analog input/output); alternate functions include SPI1_SCK, TIM3_CH1, I2C_SDA, USART1_RX, COMP2_INP, ADC_IN3, USART2_RX, EVENTOUT, SPI1_MOSI, TIM1_CH1 and I2C_SCL. |
| 20 | PA4 | bidirectional | COM-type GPIO (normal 5 V port with analog input/output); alternate functions include SPI1_NSS, ADC_IN4, USART1_CK, TIM14_CH1, USART2_CK, EVENTOUT, RTC_OUT, TIM3_CH3 and USART2_TX. |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | PUYA |
| Package | QFN-20-EP(3x3) |
| Category | Embedded Processors & Controllers |
| Pins | 21 |
CAD (KiCad official)
- Symbol:
PY32F003F16U6TR - Footprint:
Package_DFN_QFN:UQFN-20-1EP_3x3mm_P0.4mm_EP1.85x1.85mm - 3D model: QFN-20-EP(3x3) (KiCad packages3D, STEP)
- 3D model files:
py32f003f16u6tr-etched.step/py32f003f16u6tr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);py32f003f16u6tr.step/py32f003f16u6tr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: PUYA datasheet (43 pp, sha256
c1a03b8b328379d1, retrieved 2026-10-09, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).