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TPS65270RGER

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Texas Instruments DC-DC Converters, VQFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management (pmic)tps65270rgerfactory-2.0.0extractor-text
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TPS65270RGER

Texas Instruments · DC-DC Converters · VQFN-24-EP(4x4)

TPS65270RGER from Texas Instruments, in a VQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SS2 passive Soft-start input for Buck 2; an internal 5-µA charging current sources into this pin, and a small ceramic capacitor on it sets the Buck 2 soft-start time.
2 FB2 input Feedback voltage input for Buck 2; a resistor divider sets 0.8 V at FB2 from the converter output to ground, and the absolute maximum voltage on this pin is -0.3 to 3.6 V.
3 EN2 input Enable for Buck 2: logic high enables Buck 2 and logic low disables it, with a weak internal pull-up to V5V if left open for automatic enable and a small ceramic capacitor to ground for delayed start-up; absolute maximum voltage is -0.3 to 7 V.
4 BST2 passive Bootstrap supply for the Buck 2 high-side gate driver, connected through a 47-nF ceramic capacitor to the LX2 switching node; BST2 is rated -0.3 to 7 V referenced to LX2.
5 VIN2 power_in Input supply for Buck 2 with a 10-µF ceramic capacitor placed close to this pin; operating input voltage range is 4.5 V to 18 V.
6 LX2 output Switching node connecting to the Buck 2 inductor; withstands -1 to 18 V transients below 10 ns.
7 LX2 output Switching node connecting to the Buck 2 inductor (second LX2 pin, bonded in parallel with pin 6).
8 GND power_in Power ground for Buck 1 and Buck 2; absolute maximum voltage range is -0.3 to 0.3 V.
9 GND power_in Power ground for Buck 1 and Buck 2; absolute maximum voltage range is -0.3 to 0.3 V.
10 GND power_in Power ground for Buck 1 and Buck 2; absolute maximum voltage range is -0.3 to 0.3 V.
11 GND power_in Power ground for Buck 1 and Buck 2; absolute maximum voltage range is -0.3 to 0.3 V.
12 LX1 output Switching node connecting to the Buck 1 inductor; withstands -1 to 18 V transients below 10 ns.
13 LX1 output Switching node connecting to the Buck 1 inductor (second LX1 pin, bonded in parallel with pin 12).
14 VIN1 power_in Input supply for Buck 1 with a 10-µF ceramic capacitor placed close to this pin; operating input voltage range is 4.5 V to 18 V.
15 BST1 passive Bootstrap supply for the Buck 1 high-side gate driver, connected through a 47-nF ceramic capacitor to the LX1 switching node; BST1 is rated -0.3 to 7 V referenced to LX1.
16 EN1 input Enable for Buck 1: logic high enables Buck 1 and logic low disables it, with a weak internal pull-up to V5V if left open for automatic enable and a small ceramic capacitor to ground for delayed start-up; absolute maximum voltage is -0.3 to 7 V.
17 FB1 input Feedback voltage input for Buck 1; a resistor divider sets 0.8 V at FB1 from the converter output to ground, and the absolute maximum voltage on this pin is -0.3 to 3.6 V.
18 SS1 passive Soft-start input for Buck 1; an internal 5-µA charging current sources into this pin, and a small ceramic capacitor on it sets the Buck 1 soft-start time.
19 COMP1 passive Loop compensation pin for Buck 1; a series RC network connected here compensates the control loop of this converter.
20 LOW_P input Low-power mode select: high enables pulse-skipping at light load for Buck 1 and Buck 2, low forces both to PWM mode; the pin must not be left open and is rated -0.3 to 7 V.
21 VCC power_out Internal 6.5-V power supply bias; connect a 10-µF ceramic capacitor from this pin to ground.
22 AGND power_in Analog ground; connect all GND pins and the power pad together, and tie AGND directly to the power pad under the IC.
23 ROSC passive Oscillator frequency setup; a resistor from this pin to ground sets the internal oscillator clock frequency between 300 kHz and 1.4 MHz, with a rated voltage range of -0.3 to 3.6 V.
24 COMP2 passive Loop compensation pin for Buck 2; a series RC network connected here compensates the control loop of this converter.
25 Thermal Pad passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-24-EP(4x4)
Category Power Management (PMIC)
Pins 25

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input voltage range VIN1 and VIN2 VIN 4.5 18 V 7
UVLO rising VIN 4 4.2 4.45 V Rising VIN 7
UVLO falling VIN 3.65 3.85 4.1 V Falling VIN 7
Regulated feedback voltage VFB tolerance, TJ = 25°C VFB -1 1 % VIN = 12 V, VCOMP = 1.2 V, TJ = 25°C 7
Regulated feedback voltage VFB tolerance, TJ = -40°C to 125°C VFB -2 2 % VIN = 12 V, VCOMP = 1.2 V, TJ = -40°C to 125°C 7
Switching frequency range FSW_BK 0.3 1.4 MHz Set by external resistor ROSC 7
Programmable switching frequency FSW 0.85 1 1.15 MHz ROSC = 250 kΩ 7
Programmable switching frequency FSW 425 500 575 kHz ROSC = 500 kΩ 7
Minimum on time Ton_min 80 120 ns 7
Voltage range at VIN1, VIN2, LX1, LX2 -0.3 18 V Over operating free-air temperature range 6
Voltage range at LX1, LX2 transient -1 18 V Maximum withstand voltage transient < 10 ns 6
Voltage at BST1, BST2 referenced to LX1, LX2 -0.3 7 V Referenced to LX1, LX2 pin 6
Voltage at VCC, EN1, EN2, COMP1, COMP2, LOW_P -0.3 7 V 6
Voltage at SS1, SS2, FB1, FB2, ROSC -0.3 3.6 V 6
Voltage at AGND, GND -0.3 0.3 V 6
Operating virtual junction temperature range TJ -40 125 °C 6
Storage temperature range TSTG -55 150 °C 6
Input operating voltage VIN 4.5 18 V 6
Ambient temperature TA -40 85 °C 6
Electrostatic discharge, human body model (HBM) 2000 V Human body model (HBM) 6
Electrostatic discharge, charge device model (CDM) 500 V Charge device model (CDM) 6
Input voltage hysteresis UVLO 0.35 V 7
Shutdown supply current IDDSDN IDDSDN 10 µA EN1 = EN2 = 0 V 7
Non switching quiescent power supply current IDDQ_nsw 1 mA VFB1 = VFB2 = 900 mV, LOW_P = high 7
VCC internal biasing supply 6.25 V VCC load current = 0 A, VIN = 12 V 7
VCC LDO drop-out voltage VCC_drop 180 mV VIN = 5 V, VCC load current = 20 mA 7
VCC current limit IVCC 200 mA 4.5 V < VIN < 18 V 7
Regulated feedback voltage VFB VFB 0.8 V VIN = 12 V, VCOMP = 1.2 V, TJ = 25°C 7
Line regulation DC 0.5 %/V VIN = 4.5 V to 18 V, IOUT = 1 A 7
Load regulation DC 0.4 %/A IOUT = 10% - 90% IOUT,MAX 7
Error amplifier transconductance Gm_EA 130 µs -2 µA < ICOMP < 2 µA 7
COMP voltage to inductor current transconductance Gm_SRC 10 A/V ILX = 0.5 A 7
EN1 and EN2 pin threshold rising VEN 1.55 V Rising 7
EN1 and EN2 pin threshold falling VEN 0.4 V Falling 7
PSM low power mode threshold rising VPSM 1.55 V Rising 7
PSM low power mode threshold falling VPSM 0.4 V Falling 7
SS1 and SS2 soft-start charging current ISS 5 µA 7
Buck 1 peak inductor current limit ILIMIT1 3.2 A 4.5 V < VIN < 18 V 7
Buck 1 low side MOSFET current limit ILIMIT1_LS1 2 A 4.5 V < VIN < 18 V 7
Buck 2 peak inductor current limit ILIMIT2 4.1 A 4.5 V < VIN < 18 V 7
Buck 2 low side MOSFET current limit ILIMIT1_LS2 2 A 4.5 V < VIN < 18 V 7
On resistance of high side FET on CH1 Rdson_HS1 120 mΩ BST1 to LX1 = 6.25 V 7
On resistance of low side FET on CH1 Rdson_LS1 80 mΩ VIN = 12 V 7
On resistance of high side FET on CH2 Rdson_HS2 95 mΩ BST2 to LX2 = 6.25 V 7
On resistance of low side FET on CH2 Rdson_LS2 50 mΩ VIN = 12 V 7
Thermal protection trip point TTRIP 160 °C Rising temperature 7
Thermal protection hysteresis THYST 20 °C 7
Junction-to-ambient thermal resistance θJA 32.6 °C/W JEDEC JESD 51-5 high-K board with thermal vias 6
Junction-to-case thermal resistance θJC 10 °C/W Junction to exposed pad 6

CAD (KiCad official)

  • Symbol: TPS65270RGER
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.7mm
  • 3D model: VQFN-24-EP(4x4) (KiCad packages3D, STEP)
  • 3D model files: tps65270rger-etched.step / tps65270rger-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps65270rger.step / tps65270rger.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (29 pp, sha256 5c940e7eff8ac8fe, retrieved 2026-10-08, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF