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ACPL-C784-500E
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Broadcom AVAGO Logic Output Optoisolators, SO-8-6.8mm. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownACPL-C784-500E
Broadcom AVAGO · Logic Output Optoisolators · SO-8-6.8mm
ACPL-C784-500E from Broadcom AVAGO, in a SO-8-6.8mm. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD1 | power_in | Input-side supply voltage, 4.5 V to 5.5 V relative to GND1, with a 0.1 µF bypass capacitor required between pins 1 and 4. |
| 2 | VIN+ | power_in | Positive input, with ±200 mV recommended for linear and accurate operation. |
| 3 | VIN- | power_in | Negative input, normally connected to GND1 (pin 4). |
| 4 | GND1 | power_in | Input-side ground, the reference for VDD1 and VIN-. |
| 5 | GND2 | power_in | Output-side ground, the reference for VDD2 and the outputs, with a 0.1 µF bypass capacitor required between pins 5 and 8. |
| 6 | VOUT- | output | Negative differential output, which together with VOUT+ carries the amplified input signal. |
| 7 | VOUT+ | output | Positive differential output, which together with VOUT- carries the amplified input signal. |
| 8 | VDD2 | power_in | Output-side supply voltage, 4.5 V to 5.5 V relative to GND2, with a 0.1 µF bypass capacitor required between pins 5 and 8. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Broadcom AVAGO |
| Package | SO-8-6.8mm |
| Category | Optoisolators |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Offset Voltage | VOS | -2 | 0.3 | 2 | mV | TA = 25°C | 6 |
| Input Offset Voltage | VOS | -3 | 3 | mV | TA = -40°C to +85°C | 6 | |
| Magnitude of Input Offset Change vs. Temperature | /dVOS/dTA/ | 3 | 10 | µV/°C | 6 | ||
| Gain (ACPL-C784, ±5%) | G5 | 7.6 | 8 | 8.4 | V/V | VIN+ = -200 mV to +200 mV, TA = 25°C | 6 |
| VOUT Nonlinearity over ±200 mV Input Voltage | NL200 | 0.0037 | 0.35 | % | VIN+ = -200 mV to +200 mV | 6 | |
| VOUT Nonlinearity over ±100 mV Input Voltage | NL100 | 0.0027 | 0.2 | % | VIN+ = -100 mV to +100 mV | 6 | |
| Input Side Supply Current | IDD1 | 11 | 16 | mA | VIN+ = +400 mV | 6 | |
| Output Side Supply Current | IDD2 | 13 | 16 | mA | VIN+ = -400 mV | 6 | |
| Input Current | IIN+ | -5 | -0.5 | µA | VIN+ = 0, VIN- = 0 V | 6 | |
| VOUT Output Common-Mode Voltage | VOCM | 2.2 | 2.545 | 2.8 | V | 6 | |
| Small-Signal Bandwidth (-3 dB) | f-3 dB | 50 | 100 | kHz | VIN+ = 200 mVpk-pk sine wave | 7 | |
| VIN to VOUT Signal Delay (50, 10%) | tPD10 | 2.03 | 3.3 | µs | VIN+ = 0 to 150 mV step, measured at VOUT node in Figure 15 | 7 | |
| VIN to VOUT Signal Delay (50, 50%) | tPD50 | 3.47 | 5.6 | µs | VIN+ = 0 to 150 mV step, measured at VOUT node in Figure 15 | 7 | |
| VIN to VOUT Signal Delay (50, 90%) | tPD90 | 4.99 | 9.9 | µs | VIN+ = 0 to 150 mV step, measured at VOUT node in Figure 15 | 7 | |
| VOUT Rise/Fall Time (10, 90%) | tR/F | 2.96 | 6.6 | µs | VIN+ = 0 to 150 mV step, measured at VOUT node in Figure 15 | 7 | |
| Common Mode Transient Immunity | CMTI | 10 | 15 | kV/µs | VCM = 1 kV, TA = 25°C | 7 | |
| Input-Output Momentary Withstand Voltage | VISO | 5000 | Vrms | RH < 50%, t = 1 min., TA = 25°C | 7 | ||
| Storage Temperature | TS | -55 | 125 | °C | 5 | ||
| Ambient Operating Temperature (absolute) | TA | -40 | 100 | °C | 5 | ||
| Supply Voltages (absolute) | VDD1, VDD2 | 0 | 5.5 | V | 5 | ||
| Steady-State Input Voltage | VIN+, VIN- | -2 | V | 5 | |||
| Two Second Transient Input Voltage | VIN+, VIN- | -6 | V | 5 | |||
| Output Voltages (absolute) | VOUT+, VOUT- | -0.5 | V | 5 | |||
| Lead Solder Temperature | 260 | °C | 10 sec., 1.6 mm below seating plane | 5 | |||
| Ambient Operating Temperature (recommended) | TA | -40 | 85 | °C | 5 | ||
| Supply Voltages (recommended) | VDD1, VDD2 | 4.5 | 5.5 | V | 5 | ||
| Input Voltage (linear and accurate) | VIN+, VIN- | -200 | 200 | mV | 5 | ||
| Input Voltage (functional) | VIN+, VIN- | -2 | 2 | V | 5 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | will be discussed in more detail shortly). Second, the leads are typically made from a material, such as copper, which | 14 |
CAD (KiCad official)
- Symbol:
ACPL-C784-500E - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SO-8-6.8mm (KiCad packages3D, STEP)
- 3D model files:
acpl-c784-500e-etched.step/acpl-c784-500e-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);acpl-c784-500e.step/acpl-c784-500e.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Broadcom AVAGO datasheet (17 pp, sha256
e22d3e7f4b47b07e, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).