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AD5755-1ACPZ-REEL7

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Analog Devices Digital To Analog Converters (DACs), LFCSP-64(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentadc-dac-data conversionad5755-1acpz-reel7factory-2.0.0extractor-text

Verified AD5755-1ACPZ-REEL7

by Ray · last 31 Oct 2026 · 1 record · files match
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Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier mfr, 65 pinsfiles match
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  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: AD5755-1ACPZ-REEL7 · LFCSP-64(9x9) · 65 pins
  • ✓copper: 65 copper pads, none touching another net
  • ✓datasheet: all 65 pin names found in the 50-page datasheet
  • ✓distributor: lcsc C650231, digikey 505-AD5755-1ACPZ-REEL7TR-ND, mouser 584-AD5755-1ACPZR7
  • ✓family: QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-mp43lbkl/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height within the datasheet's package drawing (datasheet p.50)
  • ✓pads: 65 pins = 65 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 65 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ad5755-1acpz-reel7.kicad_sym✓ ad5755-1acpz-reel7.kicad_mod✓ ad5755-1acpz-reel7.step
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Contents

README

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AD5755-1ACPZ-REEL7

Analog Devices · Digital To Analog Converters (DACs) · LFCSP-64(9x9)

AD5755-1ACPZ-REEL7 from Analog Devices, in a LFCSP-64(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RSET_B passive Optional external precision low-drift 15 kΩ current setting resistor connection to improve IOUT_B temperature drift.
2 RSET_A passive Optional external precision low-drift 15 kΩ current setting resistor connection to improve IOUT_A temperature drift.
3 REFGND power_in Ground reference point for the internal reference.
4 REFGND power_in Ground reference point for the internal reference.
5 AD0 input Address decode input for the device under test (DUT) on the board.
6 AD1 input Address decode input for the DUT; tying both AD1 and AD0 low is not recommended when using PEC.
7 SYNC input Active-low frame synchronization input for the serial interface; data is transferred in on the falling edge of SCLK while SYNC is low.
8 SCLK input Serial clock input, data clocked in on the falling edge of SCLK at up to 30 MHz.
9 SDIN input Serial data input; data must be valid on the falling edge of SCLK.
10 SDO output Serial data output used to clock data from the serial register in readback mode.
11 DVDD power_in Digital supply, 2.7 V to 5.5 V.
12 DGND power_in Digital ground.
13 LDAC input Active-low load DAC input that updates the DAC outputs; must not be left unconnected.
14 CLEAR input Active-high edge-sensitive input that sets enabled outputs to the preprogrammed clear code; DAC output register cannot be written while active.
15 ALERT output Active-high output asserted when there has been no SPI activity for a predetermined time.
16 FAULT output Active-low open-drain output asserted on open circuit in current mode, short circuit in voltage mode, PEC error or overtemperature.
17 POC input Power-on condition input read at power-on or after reset: 0 gives tristate voltage and current channels, 1 gives a 30 kΩ pull-down on voltage output and tristate current channel.
18 RESET input Active-low hardware reset input.
19 AVDD power_in Positive analog supply, 9 V to 33 V.
20 COMPLV_A passive Optional 220 pF compensation capacitor connection to VOUT_A allowing up to 2 µF load at the cost of bandwidth and settling time.
21 CHARTA input HART input connection for DAC channel A; leave open if unused.
22 +VSENSE_A input Sense connection for the positive voltage output load connection of VOUT_A.
23 COMPDCDC_A passive Channel A dc-to-dc compensation capacitor connection, 10 nF to ground.
24 VBOOST_A passive Supply for channel A current output stage and VOUT_A stage, regulated to 15 V by the dc-to-dc converter.
25 VOUT_A output Buffered analog output voltage for DAC channel A.
26 IOUT_A output Current output pin for DAC channel A.
27 AVSS power_in Negative analog supply, 0 V to −26.4 V.
28 COMPLV_B passive Optional 220 pF compensation capacitor connection to VOUT_B allowing up to 2 µF load at the cost of bandwidth and settling time.
29 CHARTB input HART input connection for DAC channel B; leave open if unused.
30 +VSENSE_B input Sense connection for the positive voltage output load connection of VOUT_B.
31 VOUT_B output Buffered analog output voltage for DAC channel B.
32 COMPDCDC_B passive Channel B dc-to-dc compensation capacitor connection, 10 nF to ground.
33 IOUT_B output Current output pin for DAC channel B.
34 VBOOST_B passive Supply for channel B current output stage and VOUT_B stage, regulated to 15 V by the dc-to-dc converter.
35 AGND power_in Ground reference point for analog circuitry; must be connected to 0 V.
36 SWB output Switching output for channel B dc-to-dc circuitry.
37 GNDSWB power_in Ground connection for dc-to-dc switching circuit; must always be connected to ground.
38 GNDSWA power_in Ground connection for dc-to-dc switching circuit; must always be connected to ground.
39 SWA output Switching output for channel A dc-to-dc circuitry.
40 AVSS power_in Negative analog supply, −10.8 V to −26.4 V, or 0 V in unipolar supply mode.
41 SWD output Switching output for channel D dc-to-dc circuitry.
42 GNDSWD power_in Ground connection for dc-to-dc switching circuit; must always be connected to ground.
43 GNDSWC power_in Ground connection for dc-to-dc switching circuit; must always be connected to ground.
44 SWC output Switching output for channel C dc-to-dc circuitry.
45 AVCC power_in Supply for dc-to-dc circuitry.
46 VBOOST_C passive Supply for channel C current output stage and VOUT_C stage, regulated to 15 V by the dc-to-dc converter.
47 IOUT_C output Current output pin for DAC channel C.
48 COMPDCDC_C passive Channel C dc-to-dc compensation capacitor connection, 10 nF to ground.
49 VOUT_C output Buffered analog output voltage for DAC channel C.
50 +VSENSE_C input Sense connection for the positive voltage output load connection of VOUT_C.
51 CHARTC input HART input connection for DAC channel C; leave open if unused.
52 COMPLV_C passive Optional 220 pF compensation capacitor connection to VOUT_C allowing up to 2 µF load at the cost of bandwidth and settling time.
53 AVSS power_in Negative analog supply pin.
54 IOUT_D output Current output pin for DAC channel D.
55 VOUT_D output Buffered analog output voltage for DAC channel D.
56 VBOOST_D passive Supply for channel D current output stage and VOUT_D stage, regulated to 15 V by the dc-to-dc converter.
57 COMPDCDC_D passive Channel D dc-to-dc compensation capacitor connection, 10 nF to ground.
58 +VSENSE_D input Sense connection for the positive voltage output load connection of VOUT_D.
59 CHARTD input HART input connection for DAC channel D; leave open if unused.
60 COMPLV_D passive Optional 220 pF compensation capacitor connection to VOUT_D allowing up to 2 µF load at the cost of bandwidth and settling time.
61 REFIN input External reference voltage input.
62 REFOUT output Internal reference voltage output with 0.1 µF to REFGND; must be connected to REFIN to use the internal reference.
63 RSET_D passive Optional external precision low-drift 15 kΩ current setting resistor connection to improve IOUT_D temperature drift.
64 RSET_C passive Optional external precision low-drift 15 kΩ current setting resistor connection to improve IOUT_C temperature drift.
65 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Analog Devices
Package LFCSP-64(9x9)
Category ADC/DAC/Data Conversion
Pins 65

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Voltage output TUE TUE -0.04 0.04 % FSR Bipolar supply AVSS = -15 V, loaded and unloaded 5
Voltage output TUE at 25°C TUE -0.03 0.0032 0.03 % FSR TA = 25°C 5
Voltage output INL INL -0.006 0.0012 0.006 % FSR 0 V to 5 V, 0 V to 10 V, ±5 V, ±10 V ranges 5
Voltage output INL overranges INL -0.008 0.0012 0.008 % FSR On overranges 5
Voltage output DNL DNL -1 1 LSB Guaranteed monotonic 5
Zero-scale error -0.03 0.002 0.03 % FSR 5
Bipolar zero error -0.03 0.002 0.03 % FSR 5
Offset error (voltage) -0.03 0.002 0.03 % FSR 5
Gain error (voltage) -0.03 0.004 0.03 % FSR 5
Full-scale error (voltage) -0.03 0.002 0.03 % FSR 5
Unipolar supply TUE TUE -0.06 0.025 0.06 % FSR AVSS = 0 V 5
Unipolar supply INL INL -0.009 0.009 % FSR AVSS = 0 V 5
Unipolar supply DNL DNL -1 1 LSB Guaranteed monotonic 5
Unipolar zero-scale error 0.22 % FSR AVSS = 0 V 5
Unipolar offset error -0.07 0.025 0.07 % FSR AVSS = 0 V 5
Unipolar gain error -0.07 0.015 0.07 % FSR AVSS = 0 V 5
Unipolar full-scale error -0.06 0.015 0.06 % FSR AVSS = 0 V 5
Current TUE (external RSET) TUE -0.05 0.009 0.05 % FSR External RSET 6
Current INL (external RSET) INL -0.006 0.006 % FSR External RSET 6
Current DNL (external RSET) DNL -1 1 LSB Guaranteed monotonic 6
Current offset error (external RSET) -0.05 0.005 0.05 % FSR External RSET 6
Current gain error (external RSET) -0.05 0.004 0.05 % FSR External RSET 6
Current full-scale error (external RSET) -0.05 0.008 0.05 % FSR External RSET 6
Current TUE (internal RSET) TUE -0.14 0.14 % FSR Internal RSET 6
Current TUE (internal RSET) at 25°C TUE -0.11 0.009 0.11 % FSR TA = 25°C 6
Current INL (internal RSET) INL -0.006 0.006 % FSR Internal RSET 6
Current INL (internal RSET) at 25°C INL -0.004 0.004 % FSR TA = 25°C 6
Current offset error (internal RSET) -0.05 0.05 % FSR Internal RSET 6
Current offset error (internal RSET) at 25°C -0.04 0.007 0.04 % FSR TA = 25°C 6
Current gain error (internal RSET) -0.12 0.12 % FSR Internal RSET 6
Current gain error (internal RSET) at 25°C -0.06 0.002 0.06 % FSR TA = 25°C 6
Current full-scale error (internal RSET) -0.14 0.14 % FSR Internal RSET 6
Current full-scale error (internal RSET) at 25°C -0.1 0.007 0.1 % FSR TA = 25°C 6
Reference input voltage 4.95 5 5.05 V For specified performance 7
Reference output voltage 4.995 5 5.005 V TA = 25°C 7
Reference TC -10 5 10 ppm/°C 7
Oscillator frequency 11.5 13 14.5 MHz 7
Input high voltage VIH 2 V JEDEC compliant 7
Input low voltage VIL 0.8 V JEDEC compliant 7
Digital input current -1 1 µA Per pin 7
SDO/ALERT output low voltage VOL 0.4 V Sinking 200 µA 7
SDO/ALERT high impedance leakage current -1 1 µA 7
FAULT output low voltage VOL 0.4 V 10 kΩ pull-up resistor to DVDD 7
FAULT output low voltage at 2.5 mA VOL 0.6 V At 2.5 mA 7
AVDD supply AVDD 9 33 V 7
AVSS supply AVSS -26.4 V 7
DVDD supply DVDD 2.7 5.5 V 7
AVCC supply AVCC 4.5 5.5 V 7
AIDD voltage output mode AIDD 8.6 10.5 mA Voltage output mode on all channels, output unloaded, over supplies 8
DICC DICC 4 6 mA VIH = DVDD, VIL = DGND, internal oscillator running, over supplies 8
SCLK cycle time t1 50 ns 9
Operating temperature range TA -40 105 °C Industrial 12
AVDD, VBOOST_x to AGND, DGND -0.3 33 V 12
AVDD to AVSS -0.3 60 V 12
AVCC to AGND -0.3 7 V 12
DVDD to DGND -0.3 7 V 12
Storage temperature range -65 150 °C 12
Junction temperature TJ max 125 °C 12
Thermal impedance 64-lead LFCSP θJA 28 °C/W Based on a JEDEC 4-layer test board 12

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts copper EPAD Exposed Pad. Connect this exposed pad to the potential of the AVSS pin, or, alternatively, leave it electrically unconnected. It is recommended that the pad be thermally connected to a copper pla 15

CAD (KiCad official)

  • Symbol: AD5755-1ACPZ-REEL7
  • Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • 3D model: LFCSP-64(9x9) (KiCad packages3D, STEP)
  • 3D model files: ad5755-1acpz-reel7-etched.step / ad5755-1acpz-reel7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad5755-1acpz-reel7.step / ad5755-1acpz-reel7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (50 pp, sha256 98c402eed9506091, retrieved 2026-10-31, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF