CLCQ82C55AZ from CHIPLON, in a QFP-44(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	~{CS}	input	Active-low chip select that enables the 82C55A onto the data bus for CPU communication.
2	GND	power_in	Ground; a 0.1µF decoupling capacitor between VCC and GND is recommended.
3	A1	input	Address input that together with RD and WR selects one of the three ports or the control word register.
4	A0	input	Address input that together with RD and WR selects one of the three ports or the control word register.
5	PC7	bidirectional	Port C bit 7, 8-bit-port input/output line with bus-hold circuit.
6	PC6	bidirectional	Port C bit 6, input/output line with bus-hold circuit.
7	PC5	bidirectional	Port C bit 5, input/output line with bus-hold circuit.
8	PC4	bidirectional	Port C bit 4, input/output line with bus-hold circuit.
9	PC0	bidirectional	Port C bit 0, input/output line with bus-hold circuit.
10	PC1	bidirectional	Port C bit 1, input/output line with bus-hold circuit.
11	PC2	bidirectional	Port C bit 2, input/output line with bus-hold circuit.
12	NC	unconnected	No connection.
13	PC3	bidirectional	Port C bit 3, input/output line with bus-hold circuit.
14	PB0	bidirectional	Port B bit 0, input/output line with bus-hold high circuit.
15	PB1	bidirectional	Port B bit 1, input/output line with bus-hold high circuit.
16	PB2	bidirectional	Port B bit 2, input/output line with bus-hold high circuit.
17	NC	unconnected	No connection.
18	PB3	bidirectional	Port B bit 3, input/output line with bus-hold high circuit.
19	PB4	bidirectional	Port B bit 4, input/output line with bus-hold high circuit.
20	PB5	bidirectional	Port B bit 5, input/output line with bus-hold high circuit.
21	PB6	bidirectional	Port B bit 6, input/output line with bus-hold high circuit.
22	NC	unconnected	No connection.
23	PB7	bidirectional	Port B bit 7, input/output line with bus-hold high circuit.
24	VCC	power_in	+5V power supply pin; a 0.1µF decoupling capacitor to GND is recommended.
25	D7	bidirectional	Data bus bit 7, bidirectional three-state pin connected to the system data bus.
26	D6	bidirectional	Data bus bit 6, bidirectional three-state pin connected to the system data bus.
27	D5	bidirectional	Data bus bit 5, bidirectional three-state pin connected to the system data bus.
28	D4	bidirectional	Data bus bit 4, bidirectional three-state pin connected to the system data bus.
29	D3	bidirectional	Data bus bit 3, bidirectional three-state pin connected to the system data bus.
30	D2	bidirectional	Data bus bit 2, bidirectional three-state pin connected to the system data bus.
31	D1	bidirectional	Data bus bit 1, bidirectional three-state pin connected to the system data bus.
32	D0	bidirectional	Data bus bit 0, bidirectional three-state pin connected to the system data bus.
33	RESET	input	A high level clears the control register and sets all ports (A, B, C) to input mode with bus-hold circuits on.
34	~{WR}	input	Active-low write control signal used by the CPU to load control words and data into the 82C55A.
35	PA7	bidirectional	Port A bit 7, input/output line with bus-hold high and bus-hold low circuits.
36	PA6	bidirectional	Port A bit 6, input/output line with bus-hold high and bus-hold low circuits.
37	PA5	bidirectional	Port A bit 5, input/output line with bus-hold high and bus-hold low circuits.
38	PA4	bidirectional	Port A bit 4, input/output line with bus-hold high and bus-hold low circuits.
39	NC	unconnected	No connection.
40	PA3	bidirectional	Port A bit 3, input/output line with bus-hold high and bus-hold low circuits.
41	PA2	bidirectional	Port A bit 2, input/output line with bus-hold high and bus-hold low circuits.
42	PA1	bidirectional	Port A bit 1, input/output line with bus-hold high and bus-hold low circuits.
43	PA0	bidirectional	Port A bit 0, input/output line with bus-hold high and bus-hold low circuits.
44	~{RD}	input	Active-low read control signal used by the CPU to read status information or data via the data bus.

Key specifications

Parameter	Value
Manufacturer	CHIPLON
Package	QFP-44(10x10)
Category	Interface
Pins	44

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
逻辑“1”输入电压 (VIH)	VIH	2.2			V		18
逻辑“0”输入电压 (VIL)	VIL			0.8	V		18
逻辑“1”输出电压 (VOH)	VOH	3			V	IOH = -2.5mA	18
逻辑“0”输出电压 (VOL)	VOL			0.4	V	IOL = +2.5mA	18
输入漏电流 (II)	II	-1		1	μA	VIN=VCC/GND, A1, A0, RESET, WR	18
I/O引脚漏电流 (IO)	IO	-10		10	μA	VO = VCC/GND, D0~D7	18
总线保持高电流 (IBHH)	IBHH	-50		-450	μA	VO = 3.0V. 端口A,B,C; TA = -55℃	18
总线保持高电流 (IBHH)	IBHH	-50		-400	μA	VO = 3.0V. 端口A,B,C; TA = +128℃	18
总线保持低电流 (IBHL)	IBHL	50		450	μA	VO = 1.0V, 只有端口A; TA = -55℃	18
总线保持低电流 (IBHL)	IBHL	50		400	μA	VO = 1.0V, 只有端口A; TA = +128℃	18
Darlington驱动电流 (IDAR)	IDAR	-2.5			mA	端口A，B，C。测试条件3	18
待机电源电流 (ICCSB)	ICCSB			10	μA	VCC = 5.5V，VIN = VCC或GND。输出打开	18
工作电源电流 (ICCOP)	ICCOP			1	mA/MHz	TA = + 25°C，VCC = 5.0V，典型值（见注3）	18
电源电压 (绝对最大额定值)				8	V	TA = + 25°C	18
电压范围 (运行条件)		4.5		5.5	V		18
工作温度范围 (CLCX82C55A, 商用0~70℃)		0		70	℃		18
最高储存温度范围		-65		150	℃		18
最高引线温度（焊接10s）（仅PLCC和MQFP引线）				300	℃	焊接10s	18
读取：RD之前的地址稳定 (tAR)	tAR	0			ns		19
读取：RD之后的地址稳定 (tRA)	tRA	0			ns		19
RD脉冲宽度 (tRR)	tRR	150			ns		19
RD之后来自的有效数据 (tRD)	tRD			120	ns	测试条件 1	19
RD之后的数据浮动 (tDF)	tDF	10		75	ns	测试条件 2	19
RD和WR之间的时间 (tRV)	tRV	300			ns		19
WR之前地址稳定 (tAW)	tAW	0			ns		19
WR之后地址稳定 (tWA)	tWA	20			ns		19
WR脉冲宽度 (tWW)	tWW	100			ns		19
数据有效至WR高 (tDW)	tDW	100			ns		19
WR高后数据有效 (tWD)	tWD	30			ns		19
WR=1至输出 (tWB)	tWB			350	ns	测试条件 1	19
RD之前的外围数据 (tIR)	tIR	0			ns		19
RD之后的外围数据 (tHR)	tHR	0			ns		19
ACK脉冲宽度 (tAK)	tAK	200			ns		19
STB脉冲宽度 (tST)	tST	100			ns		19
STB高之前的外围数据 (tPS)	tPS	20			ns		19
STB高之后的外围数据 (tPH)	tPH	50			ns		19
ACK=0至输出 (tAD)	tAD			175	ns	测试条件 1	19
ACK=1至输出悬空 (tKD)	tKD	20		250	ns	测试条件 2	19
WR=1到OBF=0 (tWOB)	tWOB			150	ns	测试条件 1	19
ACK=0到OBF=1 (tAOB)	tAOB			150	ns	测试条件 1	19
STB=0到IBF=1 (tSIB)	tSIB			150	ns	测试条件 1	19
RD=1到IBF=0 (tRIB)	tRIB			150	ns	测试条件 1	19
RD=0到INTR=0 (tRIT)	tRIT			200	ns	测试条件 1	19
STB=1到INTR=1 (tSIT)	tSIT			150	ns	测试条件 1	19
ACK=1到INTR=1 (tAIT)	tAIT			150	ns	测试条件 1	19
WR=0到INTR=0 (tWIT)	tWIT			200	ns	测试条件 1	19
复位脉冲宽度 (tRES)	tRES	500			ns	测试条件 1	19
热阻 θJA (MQFP封装，典型值)	θJA		62		℃/W	典型值，自由空气中安装于评估PC板（注1）	18

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
contacts		tin	不得用作第一针的标识标记。 2.当使用浸锡或镀锡铅皮时，应在最终引线表面的质心	27

CAD (KiCad official)

Symbol: CLCQ82C55AZ
Footprint: Package_QFP:LQFP-44_10x10mm_P0.8mm
3D model: QFP-44(10x10) (KiCad packages3D, STEP)
3D model files: clcq82c55az-etched.step / clcq82c55az-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); clcq82c55az.step / clcq82c55az.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: CHIPLON datasheet (30 pp, sha256 73d5263c850eca47, retrieved 2026-11-05, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

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CLCQ82C55AZ

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