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74HC595PW-Q100
Public Made by Adomby adom
Nexperia Shift Registers, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdown74HC595PW-Q100
Nexperia · Shift Registers · TSSOP-16
74HC595PW-Q100 from Nexperia, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Q1 | tri_state | Parallel data output from storage register stage 1; 3-state output, high-impedance OFF-state when OE is HIGH, with output current limited to ±35 mA. |
| 2 | Q2 | tri_state | Parallel data output from storage register stage 2; 3-state output, high-impedance OFF-state when OE is HIGH, with output current limited to ±35 mA. |
| 3 | Q3 | tri_state | Parallel data output from storage register stage 3; 3-state output, high-impedance OFF-state when OE is HIGH, with output current limited to ±35 mA. |
| 4 | Q4 | tri_state | Parallel data output from storage register stage 4; 3-state output, high-impedance OFF-state when OE is HIGH, with output current limited to ±35 mA. |
| 5 | Q5 | tri_state | Parallel data output from storage register stage 5; 3-state output, high-impedance OFF-state when OE is HIGH, with output current limited to ±35 mA. |
| 6 | Q6 | tri_state | Parallel data output from storage register stage 6; 3-state output, high-impedance OFF-state when OE is HIGH, with output current limited to ±35 mA. |
| 7 | Q7 | tri_state | Parallel data output from storage register stage 7; 3-state output, high-impedance OFF-state when OE is HIGH, with output current limited to ±35 mA. |
| 8 | GND | power_in | Ground reference (0 V) for all voltages in the device. |
| 9 | Q7S | output | Serial data output from shift register stage 7 for cascading devices; output current limited to ±25 mA over VO = -0.5 V to (VCC + 0.5 V). |
| 10 | MR | input | Asynchronous master reset, active LOW; a LOW resets only the shift register and does not affect the storage register. |
| 11 | SHCP | input | Shift register clock; data is shifted into the shift register on each LOW-to-HIGH transition. |
| 12 | STCP | input | Storage register clock; a LOW-to-HIGH transition transfers the shift register contents to the storage register and parallel outputs. |
| 13 | OE | input | Output enable, active LOW; a HIGH forces Qn outputs into the high-impedance OFF-state without changing register contents. |
| 14 | DS | input | Serial data input to shift register stage 0; inputs include clamp diodes, with input clamping current limited to ±20 mA. |
| 15 | Q0 | tri_state | Parallel data output from storage register stage 0; 3-state output, high-impedance OFF-state when OE is HIGH, with output current limited to ±35 mA. |
| 16 | VCC | power_in | Supply voltage; recommended 2.0 V to 6.0 V for 74HC595-Q100 (4.5 V to 5.5 V for 74HCT595-Q100), absolute maximum -0.5 V to +7 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | TSSOP-16 |
| Category | Logic |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
74HC595PW-Q100 - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
74hc595pw-q100-etched.step/74hc595pw-q100-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74hc595pw-q100.step/74hc595pw-q100.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (19 pp, sha256
ccdb88dc8760d451, retrieved 2026-10-09, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).