component
AD5624RBRMZ-3
Public Made by Adomby adom
Analog Devices Digital To Analog Converters (DACs), MSOP-10. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownAD5624RBRMZ-3
Analog Devices · Digital To Analog Converters (DACs) · MSOP-10
AD5624RBRMZ-3 from Analog Devices, in a MSOP-10. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUTA | output | Analog output voltage from DAC A; the output amplifier has rail-to-rail operation. |
| 2 | VOUTB | output | Analog output voltage from DAC B; the output amplifier has rail-to-rail operation. |
| 3 | GND | power_in | Ground reference point for all circuitry on the part. |
| 4 | VOUTC | output | Analog output voltage from DAC C; the output amplifier has rail-to-rail operation. |
| 5 | VOUTD | output | Analog output voltage from DAC D; the output amplifier has rail-to-rail operation. |
| 6 | SYNC | input | Active-low frame synchronization input that powers on the SCLK and DIN buffers; if taken high before the 24th falling edge, the write sequence is ignored. |
| 7 | SCLK | input | Serial clock input; data is clocked into the input shift register on its falling edge at rates up to 50 MHz. |
| 8 | DIN | input | Serial data input to a 24-bit shift register, clocked in on the falling edge of SCLK. |
| 9 | VDD | power_in | Power supply input operated from 2.7 V to 5.5 V, to be decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND. |
| 10 | VREFIN/VREFOUT | bidirectional | Common reference pin: reference output when the internal reference is used, reference input when an external reference is used (default is reference input). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | MSOP-10 |
| Category | Data Converters |
| Pins | 10 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Relative Accuracy (INL) | 0.5 | 1 | LSB | 3 | |||
| Differential Nonlinearity | 0.25 | LSB | Guaranteed monotonic by design | 4 | |||
| Zero-Code Error | 2 | 10 | mV | All zeroes loaded to DAC register | 3 | ||
| Offset Error | 1 | 10 | mV | 4 | |||
| Full-Scale Error | -0.1 | 1 | % of FSR | All ones loaded to DAC register | 4 | ||
| Gain Error | 1.5 | % of FSR | 4 | ||||
| Zero-Code Error Drift | 2 | μV/°C | 4 | ||||
| Gain Temperature Coefficient | 2.5 | ppm of FSR/°C | 4 | ||||
| DC Crosstalk due to full-scale output change (External Reference) | 10 | μV | External reference; due to full-scale output change, RL = 2 kΩ to GND or VDD | 4 | |||
| DC Crosstalk due to load current change (External Reference) | 10 | μV/mA | External reference; due to load current change | 4 | |||
| DC Crosstalk due to powering down (External Reference) | 5 | μV | External reference; per channel | 4 | |||
| DC Crosstalk due to full-scale output change (Internal Reference) | 25 | μV | Internal reference; due to full-scale output change, RL = 2 kΩ to GND or VDD | 4 | |||
| DC Crosstalk due to load current change (Internal Reference) | 20 | μV/mA | Internal reference; due to load current change | 4 | |||
| DC Crosstalk due to powering down (Internal Reference) | 10 | μV | Internal reference; per channel | 4 | |||
| Output Voltage Range | VOUT | 0 | V | Maximum is VDD (not a numeric value in datasheet) | 5 | ||
| Capacitive Load Stability | 2 | nF | RL = ∞ | 5 | |||
| Capacitive Load Stability | 10 | nF | RL = 2 kΩ | 5 | |||
| Reference Current | 170 | 200 | μA | VREF = VDD = 3.6 V | 5 | ||
| Reference Input Range | 0 | V | Maximum is VDD (not a numeric value in datasheet) | 5 | |||
| Output Voltage (internal reference) | 1.247 | 1.253 | V | At ambient | 5 | ||
| Reference TC | 5 | 15 | ppm/°C | MSOP package models | 5 | ||
| Input Current | 2 | μA | All digital inputs | 5 | |||
| VINL, Input Low Voltage | VINL | 0.8 | V | VDD = 3 V | 5 | ||
| VINH, Input High Voltage | VINH | 2 | V | VDD = 3 V | 5 | ||
| VDD Power Supply | VDD | 2.7 | 3.6 | V | 5 | ||
| IDD Normal Mode | IDD | 0.44 | 0.85 | mA | Internal reference off; VIH = VDD, VIL = GND, VDD = 2.7 V to 3.6 V | 5 | |
| IDD Normal Mode | IDD | 0.95 | 1.15 | mA | Internal reference on; VIH = VDD, VIL = GND, VDD = 2.7 V to 3.6 V | 5 | |
| IDD All Power-Down Modes | IDD | 0.2 | 1 | μA | All DACs powered down; VDD = 2.7 V to 3.6 V | 5 | |
| Operating Temperature Range (B grade) | TA | -40 | 105 | °C | B grade | 8 | |
| VDD to GND | VDD | -0.3 | 7 | V | 8 | ||
| VOUT to GND | VOUT | -0.3 | V | Maximum is VDD + 0.3 V | 8 | ||
| VREFIN/VREFOUT to GND | VREFIN/VREFOUT | -0.3 | V | Maximum is VDD + 0.3 V | 8 | ||
| Digital Input Voltage to GND | -0.3 | V | Maximum is VDD + 0.3 V | 8 | |||
| Operating Temperature Range (Industrial) | -40 | 105 | °C | Industrial | 8 | ||
| Storage Temperature Range | -65 | 150 | °C | 8 | |||
| Junction Temperature | TJ | 150 | °C | TJ max | 8 | ||
| SCLK cycle time | t1 | 20 | ns | SCLK cycle time | 7 | ||
| SCLK high time | t2 | 9 | ns | SCLK high time | 7 | ||
| SCLK low time | t3 | 9 | ns | SCLK low time | 7 | ||
| SYNC to SCLK falling edge setup time | t4 | 13 | ns | SYNC to SCLK falling edge setup time | 7 | ||
| Data setup time | t5 | 5 | ns | Data setup time | 7 | ||
| Data hold time | t6 | 5 | ns | Data hold time | 7 | ||
| SCLK falling edge to SYNC rising edge | t7 | 0 | ns | SCLK falling edge to SYNC rising edge | 7 | ||
| Minimum SYNC high time | t8 | 15 | ns | Minimum SYNC high time | 7 | ||
| SYNC rising edge to SCLK fall ignore | t9 | 13 | ns | SYNC rising edge to SCLK fall ignore | 7 | ||
| SCLK falling edge to SYNC fall ignore | t10 | 0 | ns | SCLK falling edge to SYNC fall ignore | 7 | ||
| DC Output Impedance | 0.5 | Ω | 5 | ||||
| Short-Circuit Current | 30 | mA | VDD = 3 V | 5 | |||
| Power-Up Time | 4 | μs | Coming out of power-down mode; VDD = 3 V | 5 | |||
| Reference Input Impedance | 26 | kΩ | 5 | ||||
| Output Impedance (reference) | 7.5 | kΩ | 5 | ||||
| DC Power Supply Rejection Ratio | PSRR | -100 | dB | DAC code = midscale; VDD = 3 V ± 10% | 4 | ||
| Thermal Impedance MSOP θJA | θJA | 142 | °C/W | MSOP package, 4-layer board | 8 | ||
| Thermal Impedance MSOP θJC | θJC | 43.7 | °C/W | MSOP package | 8 | ||
| Output Voltage Settling Time (AD5624R) | 3 | 4.5 | μs | ¼ to ¾ scale settling to ±0.5 LSB | 6 | ||
| Slew Rate | 1.8 | V/μs | 6 | ||||
| Digital-to-Analog Glitch Impulse | 10 | nV-s | 1 LSB change around major carry | 6 | |||
| Multiplying Bandwidth | 340 | kHz | VREF = 2 V ± 0.1 V p-p | 6 | |||
| Total Harmonic Distortion | THD | -80 | dB | VREF = 2 V ± 0.1 V p-p, frequency = 10 kHz | 6 | ||
| Output Noise Spectral Density | 120 | nV/√Hz | DAC code = midscale, 1 kHz | 6 |
CAD (KiCad official)
- Symbol:
AD5624RBRMZ-3 - Footprint:
Package_SO:MSOP-10_3x3mm_P0.5mm - 3D model: MSOP-10 (KiCad packages3D, STEP)
- 3D model files:
ad5624rbrmz-3-etched.step/ad5624rbrmz-3-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ad5624rbrmz-3.step/ad5624rbrmz-3.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (28 pp, sha256
a50d3043badbd5d0, retrieved 2026-10-28, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).