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CD40174BE

Public Made by Adom

by adom

lingxingic Flip Flops, DIP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Datasheet

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Contents

README

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CD40174BE

lingxingic · Flip Flops · DIP-16

CD40174BE from lingxingic, in a DIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 MR input Master reset input: per the function table, a LOW level forces all outputs O0 to O5 LOW regardless of CP and D; the pin table labels this pin 'clock input', which conflicts with the function table.
2 O0 output Buffered output of flip-flop 1, which follows D0 on the rising edge of CP and is forced LOW when MR is LOW.
3 D0 input Data input to flip-flop 1, sampled on the rising edge of CP (set-up and hold times apply per the AC characteristics).
4 D1 input Data input to flip-flop 2, sampled on the rising edge of CP (set-up and hold times apply per the AC characteristics).
5 O1 output Buffered output of flip-flop 2, which follows D1 on the rising edge of CP and is forced LOW when MR is LOW.
6 D2 input Data input to flip-flop 3, sampled on the rising edge of CP (set-up and hold times apply per the AC characteristics).
7 O2 output Buffered output of flip-flop 3, which follows D2 on the rising edge of CP and is forced LOW when MR is LOW.
8 VSS power_in Ground supply voltage (0 V); all voltages are referenced to VSS.
9 CP input Clock input; data is transferred from D to O on the rising edge of CP when MR is HIGH.
10 O3 output Buffered output of flip-flop 4, which follows D3 on the rising edge of CP and is forced LOW when MR is LOW.
11 D3 input Data input to flip-flop 4, sampled on the rising edge of CP (set-up and hold times apply per the AC characteristics).
12 O4 output Buffered output of flip-flop 5, which follows D4 on the rising edge of CP and is forced LOW when MR is LOW.
13 D4 input Data input to flip-flop 5, sampled on the rising edge of CP (set-up and hold times apply per the AC characteristics).
14 D5 input Data input to flip-flop 6, sampled on the rising edge of CP (set-up and hold times apply per the AC characteristics).
15 O5 output Buffered output of flip-flop 6, which follows D5 on the rising edge of CP and is forced LOW when MR is LOW.
16 VDD power_in Supply voltage; the recommended operating range is 3 V to 15 V.

Key specifications

Parameter Value
Manufacturer lingxingic
Package DIP-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
supply voltage (absolute maximum) VDD -0.5 18 V 5
input voltage (absolute maximum) VI -0.5 V all inputs; max printed as VDD+0.5 5
DC input current (absolute maximum) IIK -10 10 mA any one input 5
storage temperature (absolute maximum) Tstg -65 150 ℃ 5
soldering temperature (absolute maximum) TL 245 ℃ 10s, DIP 5
supply voltage (recommended operating) VDD 3 15 V 6
ambient temperature (recommended operating) Tamb -40 125 ℃ in free air 6
HIGH-level input voltage VIH 3.5 V VDD=5V; Tamb=-40 ℃ to +125 ℃ 7
HIGH-level input voltage VIH 7 V VDD=10V; Tamb=-40 ℃ to +125 ℃ 7
HIGH-level input voltage VIH 11 V VDD=15V; Tamb=-40 ℃ to +125 ℃ 7
LOW-level input voltage VIL 1.5 V VDD=5V; Tamb=-40 ℃ to +125 ℃ 7
LOW-level input voltage VIL 3 V VDD=10V; Tamb=-40 ℃ to +125 ℃ 7
LOW-level input voltage VIL 4 V VDD=15V; Tamb=-40 ℃ to +125 ℃ 7
HIGH-level output voltage VOH 4.95 V VDD=5V; /IO/<1uA; Tamb=-40 ℃ to +125 ℃ 7
HIGH-level output voltage VOH 9.95 V VDD=10V; /IO/<1uA; Tamb=-40 ℃ to +125 ℃ 7
HIGH-level output voltage VOH 14.95 V VDD=15V; /IO/<1uA; Tamb=-40 ℃ to +125 ℃ 7
LOW-level output voltage VOL 0.05 V VDD=5V; /IO/<1uA; Tamb=-40 ℃ to +125 ℃ 7
HIGH-level output current IOH -0.3 mA VDD=5V; VO=4.6V; Tamb=-40 ℃ to +125 ℃ 7
HIGH-level output current IOH -1.15 mA VDD=5V; VO=2.5V; Tamb=-40 ℃ to +125 ℃ 7
HIGH-level output current IOH -0.45 mA VDD=10V; VO=9.5V; Tamb=-40 ℃ to +125 ℃ 7
HIGH-level output current IOH -1.4 mA VDD=15V; VO=13.5V; Tamb=-40 ℃ to +125 ℃ 7
LOW-level output current IOL 0.29 mA VDD=5V; VO=0.4V; Tamb=-40 ℃ to +125 ℃ 7
LOW-level output current IOL 0.38 mA VDD=10V; VO=0.5V; Tamb=-40 ℃ to +125 ℃ 7
LOW-level output current IOL 1.2 mA VDD=15V; VO=1.5V; Tamb=-40 ℃ to +125 ℃ 7
input leakage current II -4 4 uA VDD=15V; VI=15V or GND; Tamb=-40 ℃ to +125 ℃ 7
supply current IDD 7.5 uA VDD=5V; VI=5V or GND; IO=0A; Tamb=-40 ℃ to +125 ℃ 7
supply current IDD 15 uA VDD=10V; VI=10V or GND; IO=0A; Tamb=-40 ℃ to +125 ℃ 7
supply current IDD 30 uA VDD=15V; VI=15V or GND; IO=0A; Tamb=-40 ℃ to +125 ℃ 7
propagation delay time CP to Qn tPHL, tPLH 186 ns VDD=5V; See Figure 4; Tamb=-40 ℃ to +125 ℃ 9
propagation delay time CP to Qn tPHL, tPLH 78 ns VDD=10V; See Figure 4; Tamb=-40 ℃ to +125 ℃ 9
propagation delay time CP to Qn tPHL, tPLH 54 ns VDD=15V; See Figure 4; Tamb=-40 ℃ to +125 ℃ 9
MR to Qn HIGH to LOW propagation delay time tPHL 210 ns VDD=5V; See Figure 5; Tamb=-40 ℃ to +125 ℃ 9
MR to Qn HIGH to LOW propagation delay time tPHL 84 ns VDD=10V; See Figure 5; Tamb=-40 ℃ to +125 ℃ 9
MR to Qn HIGH to LOW propagation delay time tPHL 60 ns VDD=15V; See Figure 5; Tamb=-40 ℃ to +125 ℃ 9
transition time tTHL, tTLH 144 ns VDD=5V; See Figure 4; Tamb=-40 ℃ to +125 ℃ 9
transition time tTHL, tTLH 72 ns VDD=10V; See Figure 4; Tamb=-40 ℃ to +125 ℃ 9
transition time tTHL, tTLH 48 ns VDD=15V; See Figure 4; Tamb=-40 ℃ to +125 ℃ 9
set-up time tsu 24 ns VDD=5V; See Figure 5; Tamb=-40 ℃ to +125 ℃ 9
set-up time tsu 12 ns VDD=10V; See Figure 5; Tamb=-40 ℃ to +125 ℃ 9
hold time thold 12 ns VDD=5V; Tamb=-40 ℃ to +125 ℃ 9
hold time thold 6 ns VDD=10V; Tamb=-40 ℃ to +125 ℃ 9
Minimum clock pulse width LOW tWCPL 84 ns VDD=5V; Tamb=-40 ℃ to +125 ℃ 9
Minimum clock pulse width LOW tWCPL 36 ns VDD=10V; Tamb=-40 ℃ to +125 ℃ 9
Minimum clock pulse width LOW tWCPL 24 ns VDD=15V; Tamb=-40 ℃ to +125 ℃ 9
Minimum MR pulse width LOW tWMRL 84 ns VDD=5V; Tamb=-40 ℃ to +125 ℃ 9
Minimum MR pulse width LOW tWMRL 45 ns VDD=10V; Tamb=-40 ℃ to +125 ℃ 9
Minimum MR pulse width LOW tWMRL 30 ns VDD=15V; Tamb=-40 ℃ to +125 ℃ 9
Recovery time for MR tRMR 54 ns VDD=5V; Tamb=-40 ℃ to +125 ℃ 9
Recovery time for MR tRMR 24 ns VDD=10V; Tamb=-40 ℃ to +125 ℃ 9
Recovery time for MR tRMR 18 ns VDD=15V; Tamb=-40 ℃ to +125 ℃ 9
Maximum clock pulse frequency fmax 4 MHZ VDD=5V; Tamb=-40 ℃ to +125 ℃ 9
Maximum clock pulse frequency fmax 12 MHZ VDD=10V; Tamb=-40 ℃ to +125 ℃ 9
Maximum clock pulse frequency fmax 16 MHZ VDD=15V; Tamb=-40 ℃ to +125 ℃ 9

CAD (KiCad official)

  • Symbol: CD40174BE
  • Footprint: Package_DIP:DIP-16_W7.62mm
  • 3D model: DIP-16 (KiCad packages3D, STEP)
  • 3D model files: cd40174be-etched.step / cd40174be-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd40174be.step / cd40174be.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: lingxingic datasheet (14 pp, sha256 0841325085dd15c3, retrieved 2026-10-15, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF