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MX25L51245GZ2I-08G
Public Made by Adomby adom
MXIC Macronix NOR FLASH, WSON-8-EP(6x8). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMX25L51245GZ2I-08G
MXIC Macronix · NOR FLASH · WSON-8-EP(6x8)
MX25L51245GZ2I-08G from MXIC Macronix, in a WSON-8-EP(6x8). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CS# | input | Chip select; serial access to the device is enabled by CS#, and the device remains in standby mode when CS# is high. |
| 2 | SO/SIO1 | bidirectional | Serial data output in single I/O mode, and bidirectional serial data SIO1 for address/dummy input and data output in 2x I/O or 4x I/O read mode. |
| 3 | WP#/SIO2 | bidirectional | Write protection, active low, used with the SRWD bit for hardware protection; becomes SIO2 in 4x I/O read mode or when QE is 1, and has an internal pull-up if not physically connected. |
| 4 | GND | power_in | Ground. |
| 5 | SI/SIO0 | bidirectional | Serial data input in single I/O mode, and bidirectional serial data SIO0 for address/dummy input and data output in 2x I/O or 4x I/O read mode. |
| 6 | SCLK | input | Serial clock input; the device supports clock frequencies up to 166MHz. |
| 7 | RESET#/SIO3 | bidirectional | Hardware reset, active low, which becomes SIO3 when QE is 1 (disabling hardware RESET on the 8-pin package) and has an internal pull-up if not physically connected. |
| 8 | VCC | power_in | 3V power supply input. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | MXIC Macronix |
| Package | WSON-8-EP(6x8) |
| Category | Memory |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Ambient Operating Temperature (industrial grade) | -40 | 85 | °C | Industrial grade | 119 | ||
| Storage Temperature | -65 | 150 | °C | 119 | |||
| Applied Input Voltage | -0.5 | V | Max printed as VCC+0.5V | 119 | |||
| Applied Output Voltage | -0.5 | V | Max printed as VCC+0.5V | 119 | |||
| VCC to Ground Potential | VCC | -0.5 | 4 | V | 119 | ||
| Supply voltage, single power supply operation (read, erase, program) | VCC | 2.7 | 3.6 | V | Read, erase and program operations | 5 | |
| Input Load Current | ILI | -2 | 2 | uA | VCC = VCC Max, VIN = VCC or GND | 121 | |
| Output Leakage Current | ILO | -2 | 2 | uA | VCC = VCC Max, VOUT = VCC or GND | 121 | |
| VCC Standby Current | ISB1 | 20 | 100 | uA | VIN = VCC or GND, CS# = VCC | 121 | |
| Deep Power-down Current | ISB2 | 20 | uA | VIN = VCC or GND, CS# = VCC | 121 | ||
| VCC Read (DTR 4 x I/O read, f=100MHz) | ICC1 | 30 | mA | f=100MHz, (DTR 4 x I/O read), SCLK=0.1VCC/0.9VCC, SO=Open | 121 | ||
| VCC Read (4 x I/O read, f=104MHz) | ICC1 | 20 | mA | f=104MHz, (4 x I/O read), SCLK=0.1VCC/0.9VCC, SO=Open | 121 | ||
| VCC Read (f=84MHz) | ICC1 | 15 | mA | f=84MHz, SCLK=0.1VCC/0.9VCC, SO=Open | 121 | ||
| VCC Program Current (PP) | ICC2 | 20 | 25 | mA | Program in Progress, CS# = VCC | 121 | |
| VCC Write Status Register (WRSR) Current | ICC3 | 20 | mA | Program status register in progress, CS#=VCC | 121 | ||
| VCC Sector/Block (32K, 64K) Erase Current (SE/BE/BE32K) | ICC4 | 20 | 25 | mA | Erase in Progress, CS#=VCC | 121 | |
| VCC Chip Erase Current (CE) | ICC5 | 20 | 25 | mA | Erase in Progress, CS#=VCC | 121 | |
| Input Low Voltage | VIL | -0.5 | 0.8 | V | 121 | ||
| Output Low Voltage | VOL | 0.2 | V | IOL = 100uA | 121 | ||
| Clock Frequency for all commands (except Read Operation) | fSCLK | 166 | MHz | 122 | |||
| Clock Frequency for READ instructions | fRSCLK | 66 | MHz | 122 | |||
| Clock High Time (others, fSCLK/fTSCLK) | tCH | 7 | ns | ≤ 66MHz | 122 | ||
| Clock Low Time (others, fSCLK/fTSCLK) | tCL | 7 | ns | ≤ 66MHz | 122 | ||
| CS# Active Setup Time (relative to SCLK) | tSLCH | 3 | ns | 122 | |||
| CS# Not Active Hold Time (relative to SCLK) | tCHSL | 4 | ns | 122 | |||
| Data In Setup Time | tDVCH/tDVCL | 2 | ns | 122 | |||
| Data In Hold Time | tCHDX/tCLDX | 2 | ns | VCC: 2.7V - 3.6V | 122 | ||
| Data In Hold Time | tCHDX/tCLDX | 1 | ns | VCC: 3.0V - 3.6V (Loading: 15pF/10pF) | 122 | ||
| CS# Active Hold Time (relative to SCLK) | tCHSH | 3 | ns | 122 | |||
| CS# Not Active Setup Time (relative to SCLK) | tSHCH | 3 | ns | 122 | |||
| CS# Deselect Time (from Read to next Read) | tSHSL | 7 | ns | 122 | |||
| CS# Deselect Time (from Write/Erase/Program to Read Status Register) | tSHSL | 30 | ns | 122 | |||
| Output Disable Time | tSHQZ | 8 | ns | 122 | |||
| Clock Low to Output Valid | tCLQV | 8 | ns | VCC: 2.7V - 3.6V, Loading: 30pF | 122 | ||
| Clock Low to Output Valid | tCLQV | 6 | ns | VCC: 2.7V - 3.6V, Loading: 15pF | 122 | ||
| Clock Low to Output Valid | tCLQV | 5 | ns | VCC: 2.7V - 3.6V, Loading: 10pF | 122 | ||
| Clock Low to Output Valid | tCLQV | 4.5 | ns | VCC: 3.0V - 3.6V, Loading: 10pF, ODS (1,1,0) | 122 | ||
| Output Hold Time | tCLQX | 1 | ns | Loading: 30pF | 122 | ||
| Write Protect Setup Time | tWHSL | 20 | ns | 122 | |||
| Write Protect Hold Time | tSHWL | 100 | ns | 122 | |||
| CS# High to Deep Power-down Mode | tDP | 10 | us | 122 | |||
| CS# High to Standby Mode without Electronic Signature Read | tRES1 | 30 | us | 122 | |||
| CS# High to Standby Mode with Electronic Signature Read | tRES2 | 30 | us | 122 | |||
| Write Status/Configuration Register Cycle Time | tW | 40 | ms | 122 | |||
| Write Extended Address Register | tWREAW | 40 | ns | 122 | |||
| Byte-Program | tBP | 25 | 60 | us | 122 | ||
| Page Program Cycle Time | tPP | 0.25 | 0.75 | ms | 122 | ||
| Sector Erase Cycle Time | tSE | 30 | 400 | ms | 123 | ||
| Block Erase (32KB) Cycle Time | tBE32 | 150 | 1000 | ms | 123 | ||
| Block Erase (64KB) Cycle Time | tBE | 280 | 2000 | ms | 123 | ||
| Chip Erase Cycle Time | tCE | 140 | 200 | s | 123 | ||
| Latency between Program Resume and next Suspend | tPRS | 0.3 | 100 | us | 123 | ||
| Latency between Erase Resume and next Suspend | tERS | 0.3 | 400 | us | 123 | ||
| Erase Suspend Latency | tESL | 25 | us | 123 | |||
| Program Suspend Latency | tPSL | 25 | us | 123 | |||
| VCC Rise Time | tVR | 1 | 500000 | us/V | 124 |
CAD (KiCad official)
- Symbol:
MX25L51245GZ2I-08G - Footprint:
Package_SON:WSON-8-1EP_8x6mm_P1.27mm_EP3.4x4.3mm - 3D model: WSON-8-EP(6x8), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.75 mm nominal WSON height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
mx25l51245gz2i-08g-etched.step/mx25l51245gz2i-08g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mx25l51245gz2i-08g.step/mx25l51245gz2i-08g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: MXIC Macronix datasheet (136 pp, sha256
051c4f71215bd59b, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).