component
CD4007UBM96
Public Made by Adomby adom
Texas Instruments Logic Gates, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCD4007UBM96
Texas Instruments · Logic Gates · SOIC-14
CD4007UBM96 from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Q2 (P) DRAIN | passive | Drain of p-channel transistor Q2, accessible for building circuits such as inverters, NOR/NAND gates. |
| 2 | Q2 (P) SOURCE | passive | Source of p-channel transistor Q2, typically tied to VDD (pin 14) in the triple-inverter configuration. |
| 3 | Q2 GATES | input | Common gate input of transistor pair Q2; input voltage range -0.5V to VDD+0.5V. |
| 4 | Q2 (N) SOURCE | passive | Source of n-channel transistor Q2, typically tied to VSS (pin 7) in the triple-inverter configuration. |
| 5 | Q2 (N) DRAIN | passive | Drain of n-channel transistor Q2, accessible for building circuits such as inverters, NOR/NAND gates. |
| 6 | Q1 GATES | input | Common gate input of transistor pair Q1; input voltage range -0.5V to VDD+0.5V. |
| 7 | VSS, Q1&Q2&Q3 (N) SUBSTRATES, Q1 (N) SOURCE | power_in | Negative supply (VSS/GND), connected to the n-channel substrates of Q1, Q2 and Q3 and to the Q1 n-channel source. |
| 8 | Q1 (N) DRAIN | passive | Drain of n-channel transistor Q1, accessible for building circuits such as inverters, NOR/NAND gates. |
| 9 | Q3 (N) SOURCE | passive | Source of n-channel transistor Q3, typically tied to VSS (pin 7) in the triple-inverter configuration. |
| 10 | Q3 GATES | input | Common gate input of transistor pair Q3; input voltage range -0.5V to VDD+0.5V. |
| 11 | Q3 (P) DRAIN | passive | Drain of p-channel transistor Q3, accessible for building circuits such as inverters, NOR/NAND gates. |
| 12 | Q3 (N) DRAIN, Q3 (P) SOURCE | passive | Common connection of the Q3 n-channel drain and Q3 p-channel source, used as the Q3 output node. |
| 13 | Q1 (P) SOURCE | passive | Source of p-channel transistor Q1, accessible for building circuits such as inverters, NOR/NAND gates. |
| 14 | VDD, Q1&Q2&Q3 (P) SUBSTRATES, Q1 (P) DRAIN | power_in | Positive supply (VDD, 3V to 18V recommended, -0.5V to +20V absolute max), connected to the p-channel substrates of Q1, Q2 and Q3 and to the Q1 p-channel drain. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-14 |
| Category | Logic |
| Pins | 14 |
CAD (KiCad official)
- Symbol:
CD4007UBM96 - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files:
cd4007ubm96-etched.step/cd4007ubm96-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd4007ubm96.step/cd4007ubm96.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (19 pp, sha256
65236593a77ad9fa, retrieved 2026-10-18, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).