component
ST25DV64K-IER8T3
Public Made by Adomby adom
STMicroelectronics RF Chips, TSSOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownST25DV64K-IER8T3
STMicroelectronics · RF Chips · TSSOP-8
ST25DV64K-IER8T3 from STMicroelectronics, in a TSSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | V_EH | power_out | Energy harvesting analog output pin that can power external components, referenced to VSS. |
| 2 | AC0 | passive | Antenna coil connection to the RF interface (internal tuning capacitance 28.5 pF). |
| 3 | AC1 | passive | Antenna coil connection to the RF interface (internal tuning capacitance 28.5 pF). |
| 4 | VSS | power_in | Ground, the reference for VCC supply voltage and V_EH analog output voltage. |
| 5 | SDA | bidirectional | I2C serial data, open drain output that needs a pull-up resistor to VCC and may be wire-OR'ed with other open drain or open collector signals on the bus. |
| 6 | SCL | input | I2C serial clock input that strobes all data in and out of the device, needing a pull-up resistor to VCC. |
| 7 | GPO | output | Interrupt output (open drain on the 8-pin packages) configurable on RF events such as field change, memory write, activity and Fast Transfer end. |
| 8 | VCC | power_in | Supply voltage pin connected to an external DC supply, 1.8 V to 5.5 V single supply. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | TSSOP-8 |
| Category | RF & Radio |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Storage temperature (TSSOP8) | TSTG | -65 | 150 | °C | 138 | ||
| I2C input or output voltage range | VIO | -0.5 | 6.5 | V | 138 | ||
| Supply voltage VCC (absolute maximum) | VCC | -0.5 | 6.5 | V | 138 | ||
| DC output current on pin SDA | IOL_MAX_SDA | 5 | mA | when equal to 0 | 138 | ||
| DC output current on pin GPO open drain | IOL_MAX_GPO_OD | 1.5 | mA | when equal to 0 | 138 | ||
| RF input voltage amplitude peak to peak between AC0 and AC1 | VMAX_1 | 11 | V | VSS pin left floating | 138 | ||
| AC voltage between AC0 and VSS, or AC1 and VSS | VMAX_2 | -0.5 | 5.5 | V | 138 | ||
| Electrostatic discharge voltage (human body model) | VESD | 2000 | V | All pins | 138 | ||
| I2C supply voltage | VCC | 1.8 | 5.5 | V | 139 | ||
| Ambient operating temperature, I2C (SO8N, TSSOP8) | TA | -40 | 125 | °C | I2C interface | 139 | |
| Ambient operating temperature, RF interface (Range 8) | TA | -40 | 105 | °C | Range 8, RF interface | 148 | |
| Input capacitance (SDA) | CIN | 8 | pF | SDA | 139 | ||
| Input capacitance (other pins) | CIN | 6 | pF | Other pins | 139 | ||
| Input leakage current (SCL, SDA) | ILI | -0.1 | 0.03 | 0.1 | µA | VIN = VSS or VCC, device in Standby mode | 141 |
| Output leakage current (SDA) | ILO | -0.1 | 0.03 | 0.1 | µA | SDA in Hi-Z, external voltage applied on SDA: VSS or VCC | 141 |
| Operating supply current, device select E2 address, read | ICC_E2 | 126 | 180 | µA | VCC = 1.8 V, fC = 1MHz (rise/fall time < 50 ns) | 141 | |
| Operating supply current, device select E2 address, read | ICC_E2 | 230 | 260 | µA | VCC = 3.3 V, fC = 1MHz (rise/fall time < 50 ns) | 141 | |
| Operating supply current, device select E2 address, read | ICC_E2 | 510 | 550 | µA | VCC = 5.5 V, fC = 1MHz (rise/fall time < 50 ns) | 141 | |
| Operating supply current, device select MB address, read | ICC_MB | 126 | 180 | µA | VCC = 1.8 V, fC = 1MHz (rise/fall time < 50 ns) | 141 | |
| Operating supply current, device select MB address, read | ICC_MB | 230 | 260 | µA | VCC = 3.3 V, fC = 1MHz (rise/fall time < 50 ns) | 141 | |
| Operating supply current, device select MB address, read | ICC_MB | 510 | 550 | µA | VCC = 5.5 V, fC = 1MHz (rise/fall time < 50 ns) | 141 | |
| Operating supply current, device select E2 address, write | ICC0 | 120 | 310 | µA | VCC = 1.8 V, fC = 1MHz (rise/fall time < 50 ns) | 141 | |
| Operating supply current, device select E2 address, write | ICC0 | 120 | 350 | µA | VCC = 3.3 V, fC = 1MHz (rise/fall time < 50 ns) | 141 | |
| Operating supply current, device select E2 address, write | ICC0 | 140 | 450 | µA | VCC = 5.5 V, fC = 1MHz (rise/fall time < 50 ns) | 141 | |
| Static standby supply current after power ON or device select stop or time out | ICC1_PON | 78 | 110 | µA | LPD = 0, VCC = 1.8 V | 142 | |
| Static standby supply current after power ON or device select stop or time out | ICC1_PON | 82 | 110 | µA | LPD = 0, VCC = 3.3 V | 142 | |
| Static standby supply current after power ON or device select stop or time out | ICC1_PON | 95 | 130 | µA | LPD = 0, VCC = 5.5 V | 142 | |
| Input low voltage (SDA, SCL) | VIL | -0.45 | V | VCC = 1.8 V; max is 0.25 VCC as printed | 142 | ||
| Output low voltage SDA (1 MHz) | VOL_SDA | 0.05 | 0.4 | V | IOL = 1 mA, VCC = 1.8 V | 142 | |
| Output low voltage SDA (1 MHz) | VOL_SDA | 0.08 | 0.4 | V | IOL = 2.1 mA, VCC = 3.3 V | 142 | |
| Output low voltage SDA (1 MHz) | VOL_SDA | 0.1 | 0.4 | V | IOL = 3 mA, VCC = 5.5 V | 142 | |
| Device select acknowledge (power-up) | VCC_Power_up | 1.48 | 1.7 | V | Device select acknowledge, fC = 100 kHz | 142 | |
| SCL clock frequency | fC | 0.05 | 1000 | kHz | Test conditions per Table 243 | 143 | |
| Clock pulse width high | tCHCL | 0.26 | 25000 | µs | Test conditions per Table 243; max is tCHCL timeout | 143 | |
| Clock pulse width low | tCLCH | 0.5 | 25000 | µs | Test conditions per Table 243; max is tCLCH timeout | 143 | |
| I2C timeout on Start condition | tSTART_OUT | 35 | ms | Test conditions per Table 243 | 143 | ||
| SDA (out) fall time | tDL1DL2 | 20 | 120 | ns | Test conditions per Table 243 | 143 | |
| Data in set up time | tDXCX | 0 | ns | Test conditions per Table 243 | 143 | ||
| Data in hold time | tCLDX | 0 | ns | Test conditions per Table 243 | 143 | ||
| Data out hold time | tCLQX | 100 | ns | Test conditions per Table 243 | 143 | ||
| Clock low to next data valid (access time) | tCLQV | 450 | ns | Test conditions per Table 243 | 143 | ||
| Start condition set up time | tCHDX | 250 | ns | Test conditions per Table 243 | 143 | ||
| Start condition hold time | tDLCL | 0.25 | 35000 | µs | Test conditions per Table 243; max is tDLCL timeout | 144 | |
| Stop condition set up time | tCHDH | 250 | ns | Test conditions per Table 243 | 144 | ||
| Time between Stop condition and next Start condition | tDHDL | 500 | ns | Test conditions per Table 243 | 144 | ||
| I2C write time | tW | 5.5 | ms | Test conditions per Table 243; 1 to 4 bytes in same EEPROM page | 144 | ||
| Boot time, RF OFF and LPD = 0 | tbootDC | 0.6 | ms | RF OFF and LPD = 0 | 144 | ||
| Output low voltage (GPO open drain) | VOL_GPO_OD | 0.28 | 0.4 | V | IOL = 1 mA, VCC = 1.8 V | 146 | |
| Output low voltage (GPO open drain) | VOL_GPO_OD | 0.22 | 0.4 | V | IOL = 1 mA, VCC = 3.3 V | 146 | |
| Output low voltage (GPO open drain) | VOL_GPO_OD | 0.21 | 0.4 | V | IOL = 1 mA, VCC = 5.5 V | 146 | |
| Output leakage (GPO open drain) | IL_GPO_OD | -0.15 | 0.06 | 0.15 | µA | GPO in Hi-Z, external voltage applied on GPO: VSS or VCC | 146 |
| External RF signal frequency | fCC | 13.553 | 13.56 | 13.567 | MHz | 147 | |
| Operating field according to ISO | H_ISO | 150 | 5000 | mA/m | Range 8, TA = -40 °C to 105 °C | 147 | |
| 10% carrier modulation index | MI | 10 | 30 | % | MI=(A-B)/(A+B); 150 mA/m > H_ISO > 1000 mA/m | 147 | |
| 100% carrier modulation index | MI | 95 | 100 | % | MI=(A-B)/(A+B) | 147 | |
| Time for ST25DVxxx response | t1 | 318.6 | 320.9 | 323.3 | µs | 4352/FC | 147 |
| Internal tuning capacitor | CTUN | 26.5 | 28.5 | 30.5 | pF | f = 13.56 MHz | 147 |
| RF OFF time (chip reset) | tRF_OFF | 2 | ms | Chip reset | 147 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | Grey color indicates the states where power is delivered on V_EH pin. | 43 |
CAD (KiCad official)
- Symbol:
ST25DV64K-IER8T3 - Footprint:
Package_SO:TSSOP-8_4.4x3mm_P0.65mm - 3D model: TSSOP-8 (KiCad packages3D, STEP)
- 3D model files:
st25dv64k-ier8t3-etched.step/st25dv64k-ier8t3-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);st25dv64k-ier8t3.step/st25dv64k-ier8t3.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (200 pp, sha256
ab48d75d35c11396, retrieved 2026-11-05, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).