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74HC4002PW
Public Made by Adomby adom
Nexperia Logic Gates, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdown74HC4002PW
Nexperia · Logic Gates · TSSOP-14
74HC4002PW from Nexperia, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1Y | output | Data output of gate 1 (NOR of 1A, 1B, 1C, 1D). |
| 2 | 1A | input | Data input A of gate 1. |
| 3 | 1B | input | Data input B of gate 1. |
| 4 | 1C | input | Data input C of gate 1. |
| 5 | 1D | input | Data input D of gate 1. |
| 6 | n.c. | unconnected | Not connected. |
| 7 | GND | power_in | Ground (0 V). |
| 8 | n.c. | unconnected | Not connected. |
| 9 | 2A | input | Data input A of gate 2. |
| 10 | 2B | input | Data input B of gate 2. |
| 11 | 2C | input | Data input C of gate 2. |
| 12 | 2D | input | Data input D of gate 2. |
| 13 | 2Y | output | Data output of gate 2 (NOR of 2A, 2B, 2C, 2D). |
| 14 | VCC | power_in | Supply voltage, 2.0 V to 6.0 V recommended operating range. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | TSSOP-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage (absolute maximum) | VCC | -0.5 | 7 | V | 3 | ||
| Input clamping current | IIK | -20 | 20 | mA | VI < -0.5 V or VI > VCC + 0.5 V [1] | 3 | |
| Output clamping current | IOK | -20 | 20 | mA | VO < -0.5 V or VO > VCC + 0.5 V [1] | 3 | |
| Output current | IO | -25 | 25 | mA | -0.5 V < VO < VCC + 0.5 V | 3 | |
| Supply current | ICC | 50 | mA | 3 | |||
| Ground current | IGND | -50 | mA | 3 | |||
| Storage temperature | Tstg | -65 | 150 | °C | 3 | ||
| Total power dissipation | Ptot | 500 | mW | [2] For SOT402-1 (TSSOP14): derates linearly with 7.3 mW/K above 81 °C | 3 | ||
| Supply voltage (recommended) | VCC | 2 | 5 | 6 | V | 3 | |
| Input voltage (recommended) | VI | 0 | V | 3 | |||
| Output voltage (recommended) | VO | 0 | V | 3 | |||
| Ambient temperature | Tamb | -40 | 25 | 125 | °C | 3 | |
| Input transition rise and fall rate | Δt/ΔV | 625 | ns/V | VCC = 2.0 V | 3 | ||
| Input transition rise and fall rate | Δt/ΔV | 1.67 | 139 | ns/V | VCC = 4.5 V | 3 | |
| Input transition rise and fall rate | Δt/ΔV | 83 | ns/V | VCC = 6.0 V | 3 | ||
| HIGH-level input voltage | VIH | 1.5 | 1.2 | V | VCC = 2.0 V; min at -40 °C to +125 °C, typ at 25 °C | 4 | |
| HIGH-level input voltage | VIH | 3.15 | 2.4 | V | VCC = 4.5 V; min at -40 °C to +125 °C, typ at 25 °C | 4 | |
| HIGH-level input voltage | VIH | 4.2 | 3.2 | V | VCC = 6.0 V; min at -40 °C to +125 °C, typ at 25 °C | 4 | |
| LOW-level input voltage | VIL | 0.8 | 0.5 | V | VCC = 2.0 V; max at -40 °C to +125 °C, typ at 25 °C | 4 | |
| LOW-level input voltage | VIL | 2.1 | 1.35 | V | VCC = 4.5 V; max at -40 °C to +125 °C, typ at 25 °C | 4 | |
| LOW-level input voltage | VIL | 2.8 | 1.8 | V | VCC = 6.0 V; max at -40 °C to +125 °C, typ at 25 °C | 4 | |
| HIGH-level output voltage | VOH | 1.9 | 2 | V | VI = VIH or VIL; IO = -20 μA; VCC = 2.0 V | 4 | |
| HIGH-level output voltage | VOH | 4.4 | 4.5 | V | VI = VIH or VIL; IO = -20 μA; VCC = 4.5 V | 4 | |
| HIGH-level output voltage | VOH | 5.9 | 6 | V | VI = VIH or VIL; IO = -20 μA; VCC = 6.0 V | 4 | |
| HIGH-level output voltage | VOH | 3.7 | 4.32 | V | VI = VIH or VIL; IO = -4.0 mA; VCC = 4.5 V | 4 | |
| HIGH-level output voltage | VOH | 5.2 | 5.81 | V | VI = VIH or VIL; IO = -5.2 mA; VCC = 6.0 V | 4 | |
| LOW-level output voltage | VOL | 0 | 0.1 | V | VI = VIH or VIL; IO = 20 μA; VCC = 2.0 V | 4 | |
| LOW-level output voltage | VOL | 0.15 | 0.4 | V | VI = VIH or VIL; IO = 4.0 mA; VCC = 4.5 V | 4 | |
| LOW-level output voltage | VOL | 0.16 | 0.4 | V | VI = VIH or VIL; IO = 5.2 mA; VCC = 6.0 V | 4 | |
| Input leakage current | II | -1 | 1 | μA | VI = VCC or GND; VCC = 6.0 V | 4 | |
| Supply current | ICC | 40 | μA | VI = VCC or GND; IO = 0 A; VCC = 6.0 V | 4 | ||
| Propagation delay nA, nB, nC or nD to nY | tpd | 30 | 150 | ns | VCC = 2.0 V; CL = 50 pF; see Fig. 7 | 4 | |
| Propagation delay nA, nB, nC or nD to nY | tpd | 11 | 30 | ns | VCC = 4.5 V; CL = 50 pF; see Fig. 7 | 4 | |
| Propagation delay nA, nB, nC or nD to nY | tpd | 9 | 26 | ns | VCC = 6.0 V; CL = 50 pF; see Fig. 7 | 4 | |
| Transition time nY | tt | 19 | 110 | ns | VCC = 2.0 V; CL = 50 pF; see Fig. 7 | 5 | |
| Transition time nY | tt | 7 | 22 | ns | VCC = 4.5 V; CL = 50 pF; see Fig. 7 | 5 | |
| Transition time nY | tt | 6 | 19 | ns | VCC = 6.0 V; CL = 50 pF; see Fig. 7 | 5 |
CAD (KiCad official)
- Symbol:
74HC4002PW - Footprint:
Package_SO:TSSOP-14_4.4x5mm_P0.65mm - 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files:
74hc4002pw-etched.step/74hc4002pw-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74hc4002pw.step/74hc4002pw.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (11 pp, sha256
a1065b6019aeb7ee, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).