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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

CD4042BDR

Texas Instruments · Latches · SOP-16

CD4042BDR from Texas Instruments, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	Q3B	output	Complementary (inverted) latch output for latch 3; electrically identical to Q3 but inverted, tracks D3 on the active CLOCK edge selected by POLARITY.
2	D3	input	Data input for latch 3; state is transferred to Q3/Q3B on the CLOCK transition selected by POLARITY; max input current 1 µA at 18 V.
3	D4	input	Data input for latch 4; state is transferred to Q4/Q4B on the CLOCK transition selected by POLARITY; max input current 1 µA at 18 V.
4	Q4B	output	Complementary (inverted) latch output for latch 4; valid after the active CLOCK edge; max output low/high current 120 µA typ at 10 V.
5	Q4	output	Non-inverting latch output for latch 4; follows D4 at the active CLOCK edge and holds until the next active CLOCK edge.
6	CLOCK	input	Common clock input shared by all four latches; positive-going transition is active when POLARITY=0, negative-going transition is active when POLARITY=1; minimum clock pulse width 100 ns at 5 V.
7	POLARITY	input	Polarity control input: POLARITY=0 causes data transfer on the positive-going CLOCK edge; POLARITY=1 causes data transfer on the negative-going CLOCK edge.
8	VSS	power_in	Ground reference (0 V); all signal levels are referenced to VSS.
9	Q1	output	Non-inverting latch output for latch 1; follows D1 at the active CLOCK edge and holds until the next active CLOCK edge.
10	D1	input	Data input for latch 1; state is transferred to Q1/Q1B on the CLOCK transition selected by POLARITY; max input current 1 µA at 18 V.
11	D2	input	Data input for latch 2; state is transferred to Q2/Q2B on the CLOCK transition selected by POLARITY; max input current 1 µA at 18 V.
12	Q2B	output	Complementary (inverted) latch output for latch 2; valid after the active CLOCK edge; max output low/high current 120 µA typ at 10 V.
13	Q2	output	Non-inverting latch output for latch 2; follows D2 at the active CLOCK edge and holds until the next active CLOCK edge.
14	Q1B	output	Complementary (inverted) latch output for latch 1; valid after the active CLOCK edge; propagation delay to Q 110 ns typ at 5 V.
15	Q3	output	Non-inverting latch output for latch 3; follows D3 at the active CLOCK edge and holds until the next active CLOCK edge.
16	VDD	power_in	Positive supply voltage; operating range 3 V to 18 V (absolute maximum 20 V); quiescent device current 0.02 µA typ at 5 V.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SOP-16
Category	Logic
Pins	16

CAD (KiCad official)

Symbol: CD4042BDR
Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
3D model: SOP-16 (KiCad packages3D, STEP)
3D model files: cd4042bdr-etched.step / cd4042bdr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4042bdr.step / cd4042bdr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (34 pp, sha256 ef4e092831d2b059, retrieved 2026-10-20, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF