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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

LAN9730I-ABZJ

Microchip Tech · USB Converters · QFN-56-EP(8x8)

LAN9730I-ABZJ from Microchip Tech, in a QFN-56-EP(8x8). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	nPHY_INT	output	PHY interrupt output (active-high in Internal PHY Mode, active-low input in External PHY Mode).
2	TXN	bidirectional	Ethernet transmit data negative (100Ω differential pair with TXP for 100BASE-TX transmission).
3	TXP	bidirectional	Ethernet transmit data positive (100Ω differential pair with TXN for 100BASE-TX transmission).
4	VDD33A	power_in	+3.3V analog power supply for Ethernet and USB circuits.
5	RXN	bidirectional	Ethernet receive data negative (100Ω differential pair with RXP for receiving Ethernet signals).
6	RXP	bidirectional	Ethernet receive data positive (100Ω differential pair with RXN for receiving Ethernet signals).
7	EXRES	input	External Ethernet PHY bias resistor connection point; connect 12.0 kΩ ±1.0% resistor to ground.
8	VDD33A	power_in	+3.3V analog power supply for Ethernet and USB circuits.
9	VDD12PLL	power_in	+1.2V power supply for Ethernet PLL circuits.
10	HSIC_DATA	bidirectional	HSIC bidirectional double-data-rate (DDR) data signal synchronized to HSIC_STROBE per HSIC 1.0 specification.
11	HSIC_STROBE	bidirectional	HSIC bidirectional strobe signal synchronized with HSIC_DATA per High-Speed Inter-Chip specification version 1.0.
12	VDD12A	power_in	+1.2V power supply for HSIC interface and analog circuits; must be connected to VDD12CORE.
13	TEST2	input	Test pin; must be connected to +3.3V for proper operation.
14	TXER	output	Transmit error output; shows internal MII signal in Internal PHY Mode or external PHY error in External PHY Mode.
15	VDD33A	power_in	+3.3V analog power supply for Ethernet and USB circuits.
16	USBRBIAS	input	USB bias resistor connection point for HS transmit current and termination impedance; connect 12.0 kΩ ±1.0% to ground.
17	VDD12USBPLL	power_in	+1.2V power supply for USB PLL; must be connected to VDD12CORE.
18	XI	input	External 25 MHz crystal input; can alternatively be driven by single-ended 25 MHz clock oscillator (±50ppm).
19	XO	output	External 25 MHz crystal output; leave unconnected if using single-ended clock oscillator input on XI.
20	SLEW_TUNE	input	HSIC slew rate boost configuration strap; low selects 40Ω driver impedance, high selects 50Ω (sampled at power-on).
21	VDD12CORE	power_in	+1.2V power supply for digital core logic; must be connected to VDD12USBPLL, VDD12PLL, and VDD12A.
22	MDC/GPIO2	output	Management Data Clock output for MDIO interface or GPIO2 when programmed as general purpose I/O.
23	MDIO/GPIO1	bidirectional	Management Data bidirectional signal for PHY management or GPIO1 programmable I/O; serves as PME_MODE_SEL in PME mode.
24	nRESET	input	Active-low system reset input; allows external hardware to reset device and signals PME_CLEAR in PME mode.
25	VDD33IO	power_in	+3.3V I/O power supply for I/O buffer circuits.
26	nFDX_LED/GPIO8	output	Full-Duplex indicator LED output (active-low, open-drain) or GPIO8 programmable I/O; may signal PME in External PHY+PME mode.
27	nLNKA_LED/GPIO9	output	Link Activity indicator LED output (active-low, open-drain, pulsed for activity) or GPIO9; PME_MODE_SEL in External PHY+PME mode.
28	nSPD_LED/GPIO10	output	Speed indicator LED output (active-low for 100Mbps, open-drain) or GPIO10; wakeup pin in PME mode.
29	EECLK	output	EEPROM serial clock output; must be pulled up externally for proper operation with external EEPROM.
30	EECS	output	EEPROM chip select output; external pull-down resistor recommended to prevent false selection during power-up.
31	EEDO/AUTOMDIX_EN	output	EEPROM data output (drives EEDI of external EEPROM) or Auto-MDIX enable configuration strap (latched at power-on).
32	EEDI	input	EEPROM data input from external serial EEPROM (driven by EEDO output of EEPROM).
33	TEST1	input	Test pin; must be connected to VSS (ground) for proper operation.
34	PHY_SEL	input	PHY mode selection configuration strap (latched at power-on); 0=Internal PHY (default), 1=External PHY mode.
35	VDD33IO	power_in	+3.3V I/O power supply for I/O buffer circuits.
36	nTRST/RXD0	input	JTAG test port reset (active-low) in Internal PHY Mode or receive data 0 input from external PHY in External PHY Mode.
37	TDO/nPHY_RST	output	JTAG test data output in Internal PHY Mode or PHY reset (active-low) output in External PHY Mode.
38	TCK/RXD1	input	JTAG test clock input (max 25MHz) in Internal PHY Mode or receive data 1 input from external PHY in External PHY Mode.
39	TMS/RXD2	input	JTAG test mode select in Internal PHY Mode or receive data 2 input from external PHY in External PHY Mode.
40	TDI/RXD3	input	JTAG test data input in Internal PHY Mode or receive data 3 input from external PHY in External PHY Mode.
41	RXCLK	input	Receive clock input from external PHY; can be programmed to display internal MII signal in Internal PHY Mode.
42	RXDV	input	Receive data valid input from external PHY; can be programmed to display internal MII signal in Internal PHY Mode.
43	TXEN	output	Transmit enable output to external PHY indicating valid transmit data; shows internal signal in Internal PHY Mode.
44	RXER	input	Receive error input from external PHY; can be programmed to display internal MII signal in Internal PHY Mode.
45	CRS/GPIO3	input	Carrier sense input from external PHY; can show internal MII signal in Internal PHY Mode or serve as GPIO3.
46	COL/GPIO0	input	Collision detect input from external PHY; can show internal MII signal in Internal PHY Mode or serve as GPIO0 with PME capability.
47	TXCLK	input	Transmit clock input (typically from external PHY or system oscillator) that clocks out TXD signals.
48	VDD33IO	power_in	+3.3V I/O power supply for I/O buffer circuits.
49	CORE_REG_EN	input	Internal core regulator enable; tie low to disable internal regulator (external +1.2V supply required), high to enable.
50	VDD12CORE	power_in	+1.2V power supply for digital core logic; must be connected to VDD12USBPLL, VDD12PLL, and VDD12A.
51	VDD33IO	power_in	+3.3V I/O power supply for I/O buffer circuits.
52	VDD33IO	power_in	+3.3V I/O power supply for I/O buffer circuits.
53	TXD3/GPIO7/50DRIVER_EN	output	Transmit data 3 output to external PHY; shows internal MII signal in Internal PHY Mode; GPIO7 alternative; 50DRIVER_EN HSIC impedance strap.
54	TXD2/GPIO6/PORT_SWAP	output	Transmit data 2 output to external PHY; shows internal MII signal in Internal PHY Mode; GPIO6 alternative; PORT_SWAP HSIC strap.
55	TXD1/GPIO5/RMT_WKP	output	Transmit data 1 output to external PHY; shows internal MII signal in Internal PHY Mode; GPIO5 alternative; RMT_WKP remote wakeup strap.
56	TXD0/GPIO4/EEP_DISABLE	output	Transmit data 0 output to external PHY; shows internal MII signal in Internal PHY Mode; GPIO4 alternative; EEP_DISABLE EEPROM strap.
57	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Microchip Tech
Package	QFN-56-EP(8x8)
Category	Interface
Pins	57

CAD (KiCad official)

Symbol: LAN9730I-ABZJ
Footprint: Package_DFN_QFN:QFN-56-1EP_8x8mm_P0.5mm_EP4.5x5.2mm
3D model: QFN-56-EP(8x8) (KiCad packages3D, STEP)
3D model files: lan9730i-abzj-etched.step / lan9730i-abzj-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lan9730i-abzj.step / lan9730i-abzj.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Microchip Tech datasheet (61 pp, sha256 cf250745188f25f0, retrieved 2026-09-22, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF