component

74HC157PW

Public Unreviewed

by Ray

Nexperia Signal Switches / Encoders & Decoders / Multiplexers, TSSOP-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.

componentlogic74hc157pw
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads on click. Unloads when scrolled away or the tab is hidden.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads on click. Unloads when scrolled away or the tab is hidden.

PCB Footprint

Open full view ↗
Loads on click. Unloads when scrolled away or the tab is hidden.

Datasheet

Open in new tab ↗
Loads on click. Unloads when scrolled away or the tab is hidden.
Download PDF
Contents

README

markdown

74HC157PW

Nexperia · Signal Switches / Encoders & Decoders / Multiplexers · TSSOP-16

74HC157PW from Nexperia, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S input Common data select input. HIGH selects the nI1 sources onto the nY outputs; LOW selects the nI0 sources. CMOS input levels for 74HC157.
2 1I0 input Data input from source 0 for multiplexer channel 1. Routed to output 1Y when S is LOW and E is LOW.
3 1I1 input Data input from source 1 for multiplexer channel 1. Routed to output 1Y when S is HIGH and E is LOW.
4 1Y output Multiplexer output for channel 1. Non-inverting: outputs 1I0 or 1I1 depending on S; forced LOW when E is HIGH.
5 2I0 input Data input from source 0 for multiplexer channel 2. Routed to output 2Y when S is LOW and E is LOW.
6 2I1 input Data input from source 1 for multiplexer channel 2. Routed to output 2Y when S is HIGH and E is LOW.
7 2Y output Multiplexer output for channel 2. Non-inverting: outputs 2I0 or 2I1 depending on S; forced LOW when E is HIGH.
8 GND power_in Ground reference (0 V).
9 3Y output Multiplexer output for channel 3. Non-inverting: outputs 3I0 or 3I1 depending on S; forced LOW when E is HIGH.
10 3I1 input Data input from source 1 for multiplexer channel 3. Routed to output 3Y when S is HIGH and E is LOW.
11 3I0 input Data input from source 0 for multiplexer channel 3. Routed to output 3Y when S is LOW and E is LOW.
12 4Y output Multiplexer output for channel 4. Non-inverting: outputs 4I0 or 4I1 depending on S; forced LOW when E is HIGH.
13 4I1 input Data input from source 1 for multiplexer channel 4. Routed to output 4Y when S is HIGH and E is LOW.
14 4I0 input Data input from source 0 for multiplexer channel 4. Routed to output 4Y when S is LOW and E is LOW.
15 E input Active-LOW enable input. When HIGH, forces all four outputs (1Y..4Y) LOW regardless of S and data inputs. When LOW, the multiplexer passes the selected source.
16 VCC power_in Positive supply voltage. 2.0 V to 6.0 V for 74HC157; 4.5 V to 5.5 V for 74HCT157. Decouple to GND with a 100 nF ceramic close to the pin.

Key specifications

Parameter Value
Manufacturer Nexperia
Package TSSOP-16
Category Logic
Pins 16

Ordering variants

Same part, different packaging or reel option.

  • 74HC157PW
  • 74HC157PWD
  • 74HC157PWBQ

CAD (KiCad official)

  • Symbol: 74HC157PW
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (15 pp, sha256 74a09a3b77c06c22, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF