component
LM20242MH
Public Made by Adomby adom
Texas Instruments DC-DC Converters, HTSSOP-20-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads on click. Unloads only if this page sits in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads on click. Unloads only if this page sits in the background.
PCB Footprint
Open full view ↗Loads on click. Unloads only if this page sits in the background.
Datasheet
Open in new tab ↗Loads on click. Unloads only if this page sits in the background.
README
markdownLM20242MH
Texas Instruments · DC-DC Converters · HTSSOP-20-EP
LM20242MH from Texas Instruments, in a HTSSOP-20-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SS/TRK | input | Soft-start or tracking control input; an internal 5 µA source charges the external soft-start capacitor, and leaving it open activates an internal 1 ms soft-start ramp. |
| 2 | FB | input | Feedback input to the inverting input of the error amplifier, which compares against the internal 800 mV reference. |
| 3 | PGOOD | output | Open-drain power-good output indicating the output is within tolerance; a 10 kΩ to 100 kΩ pull-up resistor is recommended if used. |
| 4 | COMP | passive | Output of the internal error amplifier and input to the PWM; the loop compensation network connects between COMP and AGND. |
| 5 | VIN | power_in | Input supply voltage with a nominal operating range of 4.5 V to 36 V (VIN to GND absolute maximum is 38 V). |
| 6 | VIN | power_in | Input supply voltage with a nominal operating range of 4.5 V to 36 V (VIN to GND absolute maximum is 38 V). |
| 7 | SW | passive | Switch node: drain of the internal synchronous rectifier NMOS and source of the internal control NMOS; SW to GND is rated -0.5 V to 38 V (-1.5 V transient for under 20 ns). |
| 8 | SW | passive | Switch node: drain of the internal synchronous rectifier NMOS and source of the internal control NMOS; SW to GND is rated -0.5 V to 38 V (-1.5 V transient for under 20 ns). |
| 9 | GND | power_in | Ground, the internal reference for the power MOSFETs. |
| 10 | GND | power_in | Ground, the internal reference for the power MOSFETs. |
| 11 | GND | power_in | Ground, the internal reference for the power MOSFETs. |
| 12 | AGND | power_in | Analog ground, the internal reference for the regulator control functions. |
| 13 | SW | passive | Switch node: drain of the internal synchronous rectifier NMOS and source of the internal control NMOS; SW to GND is rated -0.5 V to 38 V (-1.5 V transient for under 20 ns). |
| 14 | SW | passive | Switch node: drain of the internal synchronous rectifier NMOS and source of the internal control NMOS; SW to GND is rated -0.5 V to 38 V (-1.5 V transient for under 20 ns). |
| 15 | VIN | power_in | Input supply voltage with a nominal operating range of 4.5 V to 36 V (VIN to GND absolute maximum is 38 V). |
| 16 | VIN | power_in | Input supply voltage with a nominal operating range of 4.5 V to 36 V (VIN to GND absolute maximum is 38 V). |
| 17 | BOOT | passive | Bootstrap input: an internal diode from VCC charges the external capacitor connected from SW to BOOT; BOOT to SW is rated at 7 V maximum. |
| 18 | VCC | power_out | Output of the high-voltage linear regulator, tracking VIN up to about 7.2 V and regulated to approximately 5.5 V; requires a 0.1 µF to 1 µF ceramic decoupling capacitor and is output only. |
| 19 | EN | input | Enable and UVLO input; an external divider sets the line undervoltage lockout threshold, and an internal 2 µA pull-up enables the regulator if the pin is left unconnected. |
| 20 | RT | passive | Internal oscillator frequency adjust input, normally biased at 550 mV; an external resistor from RT to AGND sets the switching frequency. |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HTSSOP-20-EP |
| Category | Power Management (PMIC) |
| Pins | 21 |
CAD (KiCad official)
- Symbol:
LM20242MH - Footprint:
Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm - 3D model: HTSSOP-20-EP, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.2 mm nominal TSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
lm20242mh-etched.step/lm20242mh-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lm20242mh.step/lm20242mh.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (32 pp, sha256
860788d839eb1f90, retrieved 2026-10-08, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).