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SN65HVD1050DR

Public Made by Adom

by adom

Texas Instruments CAN Transceivers, SOIC-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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SN65HVD1050DR

Texas Instruments · CAN Transceivers · SOIC-8

SN65HVD1050DR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 TXD input CAN transmit data input from the local protocol controller. LOW drives the bus to the dominant state and HIGH allows the bus to go recessive. High-level input voltage 2.1 V min; low-level input voltage 0.8 V max. A dominant time-out is triggered by a falling edge on TXD to prevent the driver from blocking the network on a stuck-low fault.
2 GND power_in Device ground reference. All voltages (except differential I/O bus voltages) are referenced to this network ground terminal.
3 VCC power_in Transceiver 5-V supply. Recommended operating range 4.5 V to 5.5 V; absolute maximum 7 V. Bypass locally with decoupling capacitors near the pin.
4 RXD output CAN receive data output to the local protocol controller. LOW indicates a dominant bus state and HIGH indicates a recessive bus state. High-level output current -2 mA; low-level output current 2 mA.
5 VREF output Reference output voltage, nominally VCC/2, used to stabilize the output common-mode voltage point of connected nodes. Absolute maximum bus/reference voltage range -27 V to 40 V.
6 CANL bidirectional Low-level CAN bus line. Differential bus I/O with common-mode range -12 V to 12 V, bus fault protection -27 V to 40 V, and transient withstand -200 V to 200 V per ISO 7637. Typical dominant output 0.8-1.5 V.
7 CANH bidirectional High-level CAN bus line. Differential bus I/O with common-mode range -12 V to 12 V, bus fault protection -27 V to 40 V, and transient withstand -200 V to 200 V per ISO 7637. Typical dominant output 2.9-4.5 V.
8 S input Mode select pin. Logic LOW (tie to GND) places the device in high-speed normal mode; logic HIGH places the device in listen-only silent mode (driver disabled, receiver active). VIH 2.1 V min, VIL 0.8 V max.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-8
Category Interface
Pins 8

Ordering variants

Same part, different packaging or reel option.

  • SN65HVD1050DR
  • SN65HVD1050DRD

CAD (KiCad official)

  • Symbol: SN65HVD1050DR
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: sn65hvd1050dr-etched.step / sn65hvd1050dr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn65hvd1050dr.step / sn65hvd1050dr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (34 pp, sha256 41d9bb19199e2cb0, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF