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ATSAMS70Q21B-ANT
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Microchip Tech Pre-ordered MCUs, LQFP-144(20x20). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
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Datasheet
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README
markdownATSAMS70Q21B-ANT
Microchip Tech · Pre-ordered MCUs · LQFP-144(20x20)
ATSAMS70Q21B-ANT from Microchip Tech, in a LQFP-144(20x20). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 102 | PA0 | bidirectional | PIO line PA0 on VDDIO with WKUP0 wakeup, PWMC0_PWMH0, TIOA0, A17 and I2SC0_MCK functions; resets as PIO input with pull-up and Schmitt trigger. |
| 99 | PA1 | bidirectional | PIO line PA1 on VDDIO with WKUP1 wakeup, PWMC0_PWML0, TIOB0, A18 and I2SC0_CK functions; resets as PIO input with pull-up and Schmitt trigger. |
| 93 | PA2 | bidirectional | PIO line PA2 on VDDIO with WKUP2 wakeup, PWMC0_PWMH1 and DATRG functions; resets as PIO input with pull-up and Schmitt trigger. |
| 91 | PA3 | bidirectional | PIO line PA3 on VDDIO with PIODC0, TWD0, LONCOL1 and PCK2 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 77 | PA4 | bidirectional | PIO line PA4 on VDDIO with WKUP3/PIODC1, TWCK0, TCLK0 and UTXD1 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 73 | PA5 | bidirectional | PIO line PA5 on VDDIO with WKUP4/PIODC2, PWMC1_PWML3, ISI_D4 and URXD1 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 114 | PA6 | bidirectional | PIO line PA6 on VDDIO with PCK0 and UTXD1 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 35 | PA7 | bidirectional | PIO line PA7 on VDDIO, also XIN32 32.768 kHz crystal oscillator input, with PWMC0_PWMH3 function; resets in PIO high-impedance state. |
| 36 | PA8 | bidirectional | PIO line PA8 on VDDIO, also XOUT32 32.768 kHz crystal oscillator output, with PWMC1_PWMH3 and AFE0_ADTRG functions; resets in PIO high-impedance state. |
| 75 | PA9 | bidirectional | PIO line PA9 on VDDIO with WKUP6/PIODC3, URXD0, ISI_D3 and PWMC0_PWMFI0 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 66 | PA10 | bidirectional | PIO line PA10 on VDDIO with PIODC4, UTXD0, PWMC0_PWMEXTRG0 and RD functions; resets as PIO input with pull-up and Schmitt trigger. |
| 64 | PA11 | bidirectional | PIO line PA11 on VDDIO with WKUP7/PIODC5, QCS, PWMC0_PWMH0 and PWMC1_PWML0 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 68 | PA12 | bidirectional | PIO line PA12 on VDDIO with PIODC6, QIO1, PWMC0_PWMH1 and PWMC1_PWMH0 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 42 | PA13 | bidirectional | PIO line PA13 on VDDIO with PIODC7, QIO0, PWMC0_PWMH2 and PWMC1_PWML1 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 51 | PA14 | bidirectional | PIO line PA14 on VDDIO with WKUP8/PIODCEN1, QSCK, PWMC0_PWMH3 and PWMC1_PWMH1 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 49 | PA15 | bidirectional | PIO line PA15 on VDDIO with D14, TIOA1, PWMC0_PWML3 and I2SC0_WS functions; resets as PIO input with pull-up and Schmitt trigger. |
| 45 | PA16 | bidirectional | PIO line PA16 on VDDIO with D15, TIOB1, PWMC0_PWML2 and I2SC0_DI functions; resets as PIO input with pull-up and Schmitt trigger. |
| 25 | PA17 | bidirectional | PIO line PA17 on VDDIO with AFE0_AD6 analog input, QIO2, PCK1 and PWMC0_PWMH3 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 24 | PA18 | bidirectional | PIO line PA18 on VDDIO with AFE0_AD7 analog input, PWMC1_PWMEXTRG1, PCK2 and A14 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 23 | PA19 | bidirectional | PIO line PA19 on VDDIO with AFE0_AD8/WKUP9, PWMC0_PWML0, A15 and I2SC1_MCK functions; resets as PIO input with pull-up and Schmitt trigger. |
| 22 | PA20 | bidirectional | PIO line PA20 on VDDIO with AFE0_AD9/WKUP10, PWMC0_PWML1, A16 and I2SC1_CK functions; resets as PIO input with pull-up and Schmitt trigger. |
| 32 | PA21 | bidirectional | PIO line PA21 on VDDIO with AFE0_AD1/PIODCEN2, RXD1, PCK1 and PWMC1_PWMFI0 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 37 | PA22 | bidirectional | PIO line PA22 on VDDIO with PIODCCLK, RK, PWMC0_PWMEXTRG1 and NCS2 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 46 | PA23 | bidirectional | PIO line PA23 on VDDIO with SCK1, PWMC0_PWMH0, A19 and PWMC1_PWML2 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 56 | PA24 | bidirectional | PIO line PA24 on VDDIO with RTS1, PWMC0_PWMH1, A20 and ISI_PCK functions; resets as PIO input with pull-up and Schmitt trigger. |
| 59 | PA25 | bidirectional | PIO line PA25 on VDDIO with CTS1, PWMC0_PWMH2, A23 and MCCK functions; resets as PIO input with pull-up and Schmitt trigger. |
| 62 | PA26 | bidirectional | PIO line PA26 on VDDIO with DCD1, TIOA2, MCDA2 and PWMC1_PWMFI1 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 70 | PA27 | bidirectional | PIO line PA27 on VDDIO with DTR1, TIOB2, MCDA3 and ISI_D7 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 112 | PA28 | bidirectional | PIO line PA28 on VDDIO with DSR1, TCLK1, MCCDA and PWMC1_PWMFI2 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 129 | PA29 | bidirectional | PIO line PA29 on VDDIO with RI1 and TCLK2 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 116 | PA30 | bidirectional | PIO line PA30 on VDDIO with WKUP11, PWMC0_PWML2, PWMC1_PWMEXTRG0, MCDA0 and I2SC0_DO functions; resets as PIO input with pull-up and Schmitt trigger. |
| 118 | PA31 | bidirectional | PIO line PA31 on VDDIO with SPI0_NPCS1, PCK2, MCDA1 and PWMC1_PWMH2 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 21 | PB0 | bidirectional | PIO line PB0 on VDDIO with AFE0_AD10/RTCOUT0, PWMC0_PWMH0, RXD0 and TF functions; resets as PIO input with pull-up and Schmitt trigger. |
| 20 | PB1 | bidirectional | PIO line PB1 on VDDIO with AFE1_AD0/RTCOUT1, PWMC0_PWMH1, GTSUCOMP, TXD0 and TK functions; resets as PIO input with pull-up and Schmitt trigger. |
| 26 | PB2 | bidirectional | PIO line PB2 on VDDIO with AFE0_AD5, CANTX0, CTS0 and SPI0_NPCS0 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 31 | PB3 | bidirectional | PIO line PB3 on VDDIO with AFE0_AD2/WKUP12, CANRX0, PCK2, RTS0 and ISI_D2 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 105 | PB4 | bidirectional | PIO line PB4 on VDDIO, system I/O TDI at reset, with TWD1, PWMC0_PWMH2, MLBCLK and TXD1 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 109 | PB5 | bidirectional | PIO line PB5 on VDDIO, system I/O TDO/TRACESWO/WKUP13, with TWCK1, PWMC0_PWML0, MLBDAT and TD functions; reset state is output with pull-up. |
| 79 | PB6 | bidirectional | PIO line PB6 on VDDIO, system I/O SWDIO/TMS for serial wire debug and boundary scan; resets as PIO input with Schmitt trigger. |
| 89 | PB7 | bidirectional | PIO line PB7 on VDDIO, system I/O SWCLK/TCK for serial wire debug and boundary scan; resets as PIO input with Schmitt trigger. |
| 141 | PB8 | bidirectional | PIO line PB8 on VDDIO, also XOUT main crystal oscillator output; resets in PIO high-impedance state. |
| 142 | PB9 | bidirectional | PIO line PB9 on VDDIO, also XIN main crystal oscillator input; resets in PIO high-impedance state. |
| 87 | PB12 | bidirectional | PIO line PB12 on VDDIO, system I/O ERASE, with PWMC0_PWML1, GTSUCOMP and PCK0 functions; resets as PIO input with pull-down and Schmitt trigger. |
| 144 | PB13 | bidirectional | PIO line PB13 on VDDIO with DAC0 analog output, PWMC0_PWML2, PCK0 and SCK0 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 11 | PC0 | bidirectional | PIO line PC0 on VDDIO with AFE1_AD9, D0 and PWMC0_PWML0 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 38 | PC1 | bidirectional | PIO line PC1 on VDDIO with D1 and PWMC0_PWML1 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 39 | PC2 | bidirectional | PIO line PC2 on VDDIO with D2 and PWMC0_PWML2 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 40 | PC3 | bidirectional | PIO line PC3 on VDDIO with D3 and PWMC0_PWML3 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 41 | PC4 | bidirectional | PIO line PC4 on VDDIO with D4 function; resets as PIO input with pull-up and Schmitt trigger. |
| 58 | PC5 | bidirectional | PIO line PC5 on VDDIO with D5 and TIOA6 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 54 | PC6 | bidirectional | PIO line PC6 on VDDIO with D6 and TIOB6 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 48 | PC7 | bidirectional | PIO line PC7 on VDDIO with D7 and TCLK6 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 82 | PC8 | bidirectional | PIO line PC8 on VDDIO with NWR0/NWE and TIOA7 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 86 | PC9 | bidirectional | PIO line PC9 on VDDIO with NANDOE and TIOB7 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 90 | PC10 | bidirectional | PIO line PC10 on VDDIO with NANDWE and TCLK7 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 94 | PC11 | bidirectional | PIO line PC11 on VDDIO with NRD and TIOA8 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 17 | PC12 | bidirectional | PIO line PC12 on VDDIO with AFE1_AD3, NCS3, TIOB8 and CANRX1 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 19 | PC13 | bidirectional | PIO line PC13 on VDDIO with AFE1_AD1, NWAIT and PWMC0_PWMH3 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 97 | PC14 | bidirectional | PIO line PC14 on VDDIO with NCS0, TCLK8 and CANTX1 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 18 | PC15 | bidirectional | PIO line PC15 on VDDIO with AFE1_AD2, NCS1/SDCS and PWMC0_PWML3 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 100 | PC16 | bidirectional | PIO line PC16 on VDDIO with A21/NANDALE function; resets as PIO input with pull-up and Schmitt trigger. |
| 103 | PC17 | bidirectional | PIO line PC17 on VDDIO with A22/NANDCLE function; resets as PIO input with pull-up and Schmitt trigger. |
| 111 | PC18 | bidirectional | PIO line PC18 on VDDIO with A0/NBS0 and PWMC0_PWML1 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 117 | PC19 | bidirectional | PIO line PC19 on VDDIO with A1 and PWMC0_PWMH2 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 120 | PC20 | bidirectional | PIO line PC20 on VDDIO with A2 and PWMC0_PWML2 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 122 | PC21 | bidirectional | PIO line PC21 on VDDIO with A3 and PWMC0_PWMH3 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 124 | PC22 | bidirectional | PIO line PC22 on VDDIO with A4 and PWMC0_PWML3 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 127 | PC23 | bidirectional | PIO line PC23 on VDDIO with A5 and TIOA3 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 130 | PC24 | bidirectional | PIO line PC24 on VDDIO with A6, TIOB3 and SPI1_SPCK functions; resets as PIO input with pull-up and Schmitt trigger. |
| 133 | PC25 | bidirectional | PIO line PC25 on VDDIO with A7, TCLK3 and SPI1_NPCS0 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 13 | PC26 | bidirectional | PIO line PC26 on VDDIO with AFE1_AD7, A8, TIOA4 and SPI1_MISO functions; resets as PIO input with pull-up and Schmitt trigger. |
| 12 | PC27 | bidirectional | PIO line PC27 on VDDIO with AFE1_AD8, A9, TIOB4 and SPI1_MOSI functions; resets as PIO input with pull-up and Schmitt trigger. |
| 76 | PC28 | bidirectional | PIO line PC28 on VDDIO with A10, TCLK4 and SPI1_NPCS1 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 16 | PC29 | bidirectional | PIO line PC29 on VDDIO with AFE1_AD4, A11, TIOA5 and SPI1_NPCS2 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 15 | PC30 | bidirectional | PIO line PC30 on VDDIO with AFE1_AD5, A12, TIOB5 and SPI1_NPCS3 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 14 | PC31 | bidirectional | PIO line PC31 on VDDIO with AFE1_AD6, A13 and TCLK5 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 1 | PD0 | bidirectional | PIO line PD0 on VDDIO with DAC1, GTXCK, PWMC1_PWML0, SPI1_NPCS1 and DCD0 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 132 | PD1 | bidirectional | PIO line PD1 on VDDIO with GTXEN, PWMC1_PWMH0, SPI1_NPCS2 and DTR0 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 131 | PD2 | bidirectional | PIO line PD2 on VDDIO with GTX0, PWMC1_PWML1, SPI1_NPCS3 and DSR0 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 128 | PD3 | bidirectional | PIO line PD3 on VDDIO with GTX1, PWMC1_PWMH1, UTXD4 and RI0 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 126 | PD4 | bidirectional | PIO line PD4 on VDDIO with GRXDV, PWMC1_PWML2, TRACED0 and DCD2 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 125 | PD5 | bidirectional | PIO line PD5 on VDDIO with GRX0, PWMC1_PWMH2, TRACED1 and DTR2 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 121 | PD6 | bidirectional | PIO line PD6 on VDDIO with GRX1, PWMC1_PWML3, TRACED2 and DSR2 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 119 | PD7 | bidirectional | PIO line PD7 on VDDIO with GRXER, PWMC1_PWMH3, TRACED3 and RI2 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 113 | PD8 | bidirectional | PIO line PD8 on VDDIO with GMDC, PWMC0_PWMFI1 and TRACECLK functions; resets as PIO input with pull-up and Schmitt trigger. |
| 110 | PD9 | bidirectional | PIO line PD9 on VDDIO with GMDIO, PWMC0_PWMFI2 and AFE1_ADTRG functions; resets as PIO input with pull-up and Schmitt trigger. |
| 101 | PD10 | bidirectional | PIO line PD10 on VDDIO with GCRS, PWMC0_PWML0, TD and MLBSIG functions; resets as PIO input with pull-down and Schmitt trigger. |
| 98 | PD11 | bidirectional | PIO line PD11 on VDDIO with GRX2, PWMC0_PWMH0, GTSUCOMP and ISI_D5 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 92 | PD12 | bidirectional | PIO line PD12 on VDDIO with GRX3, CANTX1, SPI0_NPCS2 and ISI_D6 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 88 | PD13 | bidirectional | PIO line PD13 on VDDIO with GCOL function; resets as PIO input with pull-up and Schmitt trigger. |
| 84 | PD14 | bidirectional | PIO line PD14 on VDDIO with GRXCK function; resets as PIO input with pull-up and Schmitt trigger. |
| 106 | PD15 | bidirectional | PIO line PD15 on VDDIO with GTX2, RXD2 and NWR1/NBS1 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 78 | PD16 | bidirectional | PIO line PD16 on VDDIO with GTX3 and TXD2 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 74 | PD17 | bidirectional | PIO line PD17 on VDDIO with GTXER and SCK2 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 69 | PD18 | bidirectional | PIO line PD18 on VDDIO with NCS1/SDCS, RTS2 and URXD4 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 67 | PD19 | bidirectional | PIO line PD19 on VDDIO with NCS3, CTS2 and UTXD4 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 65 | PD20 | bidirectional | PIO line PD20 on VDDIO with PWMC0_PWMH0, SPI0_MISO and GTSUCOMP functions; resets as PIO input with pull-up and Schmitt trigger. |
| 63 | PD21 | bidirectional | PIO line PD21 on VDDIO with PWMC0_PWMH1, SPI0_MOSI, TIOA11 and ISI_D1 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 60 | PD22 | bidirectional | PIO line PD22 on VDDIO with PWMC0_PWMH2, SPI0_SPCK, TIOB11 and ISI_D0 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 57 | PD23 | bidirectional | PIO line PD23 on VDDIO with PWMC0_PWMH3 function; resets as PIO input with pull-up and Schmitt trigger. |
| 55 | PD24 | bidirectional | PIO line PD24 on VDDIO with PWMC0_PWML0, RF, TCLK11 and ISI_HSYNC functions; resets as PIO input with pull-up and Schmitt trigger. |
| 52 | PD25 | bidirectional | PIO line PD25 on VDDIO with PWMC0_PWML1, SPI0_NPCS1, URXD2 and ISI_VSYNC functions; resets as PIO input with pull-up and Schmitt trigger. |
| 53 | PD26 | bidirectional | PIO line PD26 on VDDIO with PWMC0_PWML2, TD, UTXD2 and UTXD1 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 47 | PD27 | bidirectional | PIO line PD27 on VDDIO with PWMC0_PWML3, SPI0_NPCS3, TWD2 and ISI_D8 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 71 | PD28 | bidirectional | PIO line PD28 on VDDIO with WKUP5, URXD3, TWCK2 and ISI_D9 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 108 | PD29 | bidirectional | General-purpose PIO line PD29 on VDDIO with no peripheral signal listed; resets as PIO input with pull-up and Schmitt trigger. |
| 34 | PD30 | bidirectional | PIO line PD30 on VDDIO with AFE0_AD0, UTXD3 and ISI_D10 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 2 | PD31 | bidirectional | PIO line PD31 on VDDIO with QIO3, UTXD3, PCK2 and ISI_D11 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 4 | PE0 | bidirectional | PIO line PE0 on VDDIO with AFE1_AD11, D8, TIOA9 and I2SC1_WS functions; resets as PIO input with pull-up and Schmitt trigger. |
| 6 | PE1 | bidirectional | PIO line PE1 on VDDIO with D9, TIOB9 and I2SC1_DO functions; resets as PIO input with pull-up and Schmitt trigger. |
| 7 | PE2 | bidirectional | PIO line PE2 on VDDIO with D10, TCLK9 and I2SC1_DI functions; resets as PIO input with pull-up and Schmitt trigger. |
| 10 | PE3 | bidirectional | PIO line PE3 on VDDIO with AFE1_AD10, D11 and TIOA10 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 27 | PE4 | bidirectional | PIO line PE4 on VDDIO with AFE0_AD4, D12 and TIOB10 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 28 | PE5 | bidirectional | PIO line PE5 on VDDIO with AFE0_AD3, D13 and TCLK10 functions; resets as PIO input with pull-up and Schmitt trigger. |
| 3 | VDDOUT | power_out | Voltage regulator output. |
| 5 | VDDIN | power_in | Voltage regulator input that also supplies the ADC, DAC and analog comparator; must be at the same level as VDDIO and higher than or equal to VDDCORE. |
| 8 | VREFN | power_in | Negative reference input for the analog converters, tied to the GND reference rail. |
| 9 | VREFP | power_in | Positive reference voltage input for the AFE and DAC; must rise simultaneously with VDDIO and VDDIN. |
| 83 | NRST | bidirectional | Microcontroller reset input/output, active low, with internal pull-up at reset. |
| 85 | TST | input | Test select input for JTAG boundary scan manufacturing test or Fast Flash Programming mode, with internal pull-down of about 15 kOhm. |
| 30 | VDDIO | power_in | Power supply for peripheral I/O lines, backup part, backup SRAM and oscillator pads; must be 3.0V to 3.6V for USB operation. |
| 43 | VDDIO | power_in | Power supply for peripheral I/O lines, backup part, backup SRAM and oscillator pads; must be 3.0V to 3.6V for USB operation. |
| 72 | VDDIO | power_in | Power supply for peripheral I/O lines, backup part, backup SRAM and oscillator pads; must be 3.0V to 3.6V for USB operation. |
| 80 | VDDIO | power_in | Power supply for peripheral I/O lines, backup part, backup SRAM and oscillator pads; must be 3.0V to 3.6V for USB operation. |
| 96 | VDDIO | power_in | Power supply for peripheral I/O lines, backup part, backup SRAM and oscillator pads; must be 3.0V to 3.6V for USB operation. |
| 104 | JTAGSEL | input | JTAG boundary scan selection input, active high, with internal pull-down of about 15 kOhm. |
| 29 | VDDCORE | power_in | Core power supply for the core, embedded memories and peripherals; must not exceed VDDIN and VDDIO. |
| 33 | VDDCORE | power_in | Core power supply for the core, embedded memories and peripherals; must not exceed VDDIN and VDDIO. |
| 50 | VDDCORE | power_in | Core power supply for the core, embedded memories and peripherals; must not exceed VDDIN and VDDIO. |
| 81 | VDDCORE | power_in | Core power supply for the core, embedded memories and peripherals; must not exceed VDDIN and VDDIO. |
| 107 | VDDCORE | power_in | Core power supply for the core, embedded memories and peripherals; must not exceed VDDIN and VDDIO. |
| 123 | VDDPLL | power_in | Power supply for PLLA and the fast RC oscillator; must stay within 0.6V of VDDCORE. |
| 134 | VDDUTMII | power_in | USB transceiver interface supply; must be connected to VDDIO and be 3.0V to 3.6V for USB operation. |
| 136 | HSDM | bidirectional | USB high-speed data minus (D-) line. |
| 137 | HSDP | bidirectional | USB high-speed data plus (D+) line. |
| 44 | GND | power_in | Ground for the regulator, core and peripheral I/O lines. |
| 61 | GND | power_in | Ground for the regulator, core and peripheral I/O lines. |
| 95 | GND | power_in | Ground for the regulator, core and peripheral I/O lines. |
| 115 | GND | power_in | Ground for the regulator, core and peripheral I/O lines. |
| 135 | GND | power_in | Ground for the regulator, core and peripheral I/O lines. |
| 138 | GND | power_in | Ground for the regulator, core and peripheral I/O lines. |
| 139 | VDDUTMIC | power_in | USB transceiver core supply; must always be connected even if USB is unused and stay within 0.6V of VDDCORE. |
| 140 | VBG | input | Bandgap voltage reference pin. |
| 143 | VDDPLLUSB | power_in | Power supply for the UTMI PLL and the 3 MHz to 20 MHz oscillator; noise sensitive and must be 3.0V or higher for USB operation. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | LQFP-144(20x20) |
| Category | Embedded Processors & Controllers |
| Pins | 144 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Single supply voltage (Industrial temperature devices) | VDDIO/VDDIN | 1.7 | 3.6 | V | Industrial Temperature Devices | 2 | |
| USB operation supply voltage range | VDDIO | 3 | 3.6 | V | For USB operations | 43 | |
| Operating temperature range | -40 | 105 | °C | Industrial (N) | 15 | ||
| Cortex-M7 core frequency | fMAX | 300 | MHz | Cortex-M7 processor | 16 | ||
| Bus matrix frequency | fMAX | 150 | MHz | 12-layer bus matrix | 16 | ||
| VDDCORE, VDDPLL and VDDUTMIC voltage variation | 0.6 | V | Voltage levels must not vary by more than this | 43 | |||
| VDDCORE falling slope | 20 | V/ms | Powerdown when VDDCORE is not supplied by the embedded regulator | 44 | |||
| Backup mode power consumption | 1.1 | µA | Backup mode with RTC, RTT and wakeup logic enabled | 1 | |||
| Wait mode wakeup time | 10 | µs | Wait mode, until first instruction fetched; PLL startup not included | 47 | |||
| I/O pull-up and pull-down resistance | 100 | kΩ | Typical value for all I/Os | 48 | |||
| JTAGSEL pulldown resistance | 15 | kΩ | About 15 kΩ to GND | 49 | |||
| NRST pullup resistance | 100 | kΩ | About 100 kΩ to VDDIO | 50 | |||
| ERASE pulldown resistance | 100 | kΩ | About 100 kΩ to GND | 50 |
CAD (KiCad official)
- Symbol:
ATSAMS70Q21B-ANT - Footprint:
Package_QFP:LQFP-144_20x20mm_P0.5mm - 3D model: LQFP-144(20x20) (KiCad packages3D, STEP)
- 3D model files:
atsams70q21b-ant-etched.step/atsams70q21b-ant-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);atsams70q21b-ant.step/atsams70q21b-ant.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (1943 pp, sha256
94ed9d6997caca1c, retrieved 2026-10-26, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).