component
NCP12400BBHAA1DR2G
Public Made by Adomby adom
onsemi AC-DC Controllers & Regulators, SOIC-7. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
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PCB Footprint
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Datasheet
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README
markdownNCP12400BBHAA1DR2G
onsemi · AC-DC Controllers & Regulators · SOIC-7
NCP12400BBHAA1DR2G from onsemi, in a SOIC-7. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | FAULT | input | Fault input that stops the controller when pulled up or down, with an internal current source allowing direct NTC connection for over temperature detection; restarts in autorecovery or latches depending on option. |
| 2 | FB | input | Feedback input driven by an optocoupler connected to ground for output regulation; the part enters low-consumption Off mode if the pin is pulled to GND. |
| 3 | CS | input | Current sense input for current-mode operation that offers overpower compensation adjustment and also implements over voltage protection. |
| 4 | GND | power_in | Controller ground. |
| 5 | DRV | output | Drive output for the external MOSFET, with 300/500 mA source/sink peak current capability. |
| 6 | VCC | power_in | Supply pin accepting up to 28 Vdc with overvoltage detection, connected to an external auxiliary voltage. |
| 8 | HV | input | High-voltage pin connected to the rectified ac line for start-up current source, self-supply, brown-out detection, X2 capacitor discharge and HV sensing for overpower protection; must not be connected to a dc voltage. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-7 |
| Category | Power Management ICs |
| Pins | 7 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Maximum voltage on DRV pin | -0.3 | 20 | V | DRV pin 5 | 5 | ||
| VCC supply voltage continuous | VCC | -0.3 | 36 | V | VCC pin 6 | 5 | |
| Maximum voltage on HV pin | -0.3 | 750 | V | HV pin 8 | 5 | ||
| Maximum voltage on low power pins | Vmax | -0.3 | 5.5 | V | except pin 5, 6, 8 | 5 | |
| Operating junction temperature | TJMAX | -40 | 150 | °C | 5 | ||
| Storage temperature range | TSTRGMAX | -60 | 150 | °C | 5 | ||
| Thermal resistance junction-to-air, low conductivity PCB | RJ-A | 162 | °C/W | 50 mm2 copper, SOIC-7 | 5 | ||
| Thermal resistance junction-to-air, medium conductivity PCB | RJ-A | 147 | °C/W | 100 mm2 copper | 5 | ||
| Thermal resistance junction-to-air, high conductivity PCB | RJ-A | 115 | °C/W | 650 mm2 copper | 5 | ||
| Thermal resistance junction-to-case | RJ-C | 73 | °C/W | 5 | |||
| Minimum voltage for current source operation | VHV(min) | 30 | 40 | V | 5 | ||
| HV current source current out of VCC pin | Istart1 | 0.2 | 0.5 | 0.8 | mA | VCC = 0 V | 5 |
| HV current source current out of VCC pin | Istart2 | 5 | 8 | 11 | mA | VCC = VCC(on) − 0.5 V | 5 |
| Off-state leakage current | Istart(off) | 2 | 6 | µA | VHV = 750 V, VCC = 15 V | 5 | |
| HV current source restart threshold | VCC(min) | 9.5 | 10.5 | 11.5 | V | 5 | |
| Turn-off threshold | VCC(off) | 8.4 | 8.9 | 9.3 | V | 5 | |
| Overvoltage threshold | VCC(ovp) | 25 | 26.5 | 28 | V | 5 | |
| Blanking duration on VCC(off) and VCC(ovp) detection | tVCC(blank) | 10 | µs | 5 | |||
| VCC decreasing level at which internal logic resets | VCC(reset) | 4.8 | 7 | 7.7 | V | 6 | |
| VCC level for ISTART1 to ISTART2 transition | VCC(inhibit) | 1 | 2.1 | 3 | V | 6 | |
| Internal current consumption | ICC2 | 1.1 | 1.4 | 2.1 | mA | DRV open, VFB = 3 V, 100 kHz | 6 |
| Internal current consumption | ICC4 | 2 | 2.6 | 3.4 | mA | Cdrv = 1 nF, VFB = 3 V, 100 kHz | 6 |
| Internal current consumption | ICC5 | 400 | 500 | 650 | µA | Skip or before start-up | 6 |
| Internal current consumption, fault mode | 300 | 430 | 550 | µA | Fault mode (fault or latch) | 6 | |
| Internal current consumption, off-mode | 25 | µA | Off-mode | 6 | |||
| Brown-out start threshold (option B) | VHV(start) | 102 | 111 | 120 | V | VHV going up | 6 |
| Brown-out stop threshold (option B) | VHV(stop) | 94 | 103 | 116 | V | VHV going down | 6 |
| Comparator hysteresis observed at HV pin | VHV(hyst) | 2 | 3 | 4 | V | 6 | |
| Timer duration for no line detection | tDET | 21 | 32 | 43 | ms | 6 | |
| Discharge timer duration | tDIS | 21 | 32 | 43 | ms | 6 | |
| Shunt regulator voltage at VCC during X2 discharge | VCC(dis) | 10 | 11 | 12 | V | 6 | |
| Oscillator frequency 100 kHz version | fOSC | 94 | 100 | 110 | kHz | 6 | |
| Maximum duty-ratio | DMAX | 75 | 80 | 85 | % | 6 | |
| Frequency jittering amplitude | Ajitter | -5 | 4 | 5 | kHz | in percentage of FOSC; printed ±3.0 / ±4.0 / ±5.0 | 6 |
| Frequency jittering modulation frequency | Fjitter | 85 | 125 | 165 | Hz | 6 | |
| FB threshold below which foldback starts | VFB(foldS) | 2.4 | 2.5 | 2.6 | V | TJ = 25°C | 6 |
| FB threshold below which foldback is complete | VFB(foldE) | 2.05 | 2.15 | 2.25 | V | TJ = 25°C | 6 |
| Minimum switching frequency | fOSC(min) | 25 | 28 | 31 | kHz | VFB = Vskip(in) + 0.1 | 6 |
| Rise time | trise | 40 | 70 | ns | VCC = VCC(off) + 0.2 V, CDRV = 1 nF | 7 | |
| Fall time | tfall | 30 | 60 | ns | VCC = VCC(off) + 0.2 V, CDRV = 1 nF | 7 | |
| Current capability source | IDRV(source) | 300 | mA | DRV high, VDRV = 0 V | 7 | ||
| Current capability sink | IDRV(sink) | 500 | mA | DRV low, VDRV = VCC | 7 | ||
| Clamping voltage | VDRV(clamp) | 10 | 12 | 14 | V | VCC = VCC(ovp) − 0.2 V, DRV high, RDRV = 33 k, Cload = 220 pF | 7 |
| High-state voltage drop | VDRV(drop) | 1 | V | VCC = VCC(min) + 0.2 V, RDRV = 33 k, DRV high | 7 | ||
| Maximum internal current setpoint | VILIM | 0.66 | 0.7 | 0.74 | V | VFB > 3.5 V | 7 |
| Propagation delay from VIlimit detection to DRV off | tdelay | 50 | 70 | ns | VCS = VILIM | 7 | |
| Leading edge blanking duration for VILIM | tLEB | 180 | 250 | 320 | ns | 7 | |
| Threshold for immediate fault protection activation | VCS(stop) | 0.95 | 1.05 | 1.15 | V | 7 | |
| Leading edge blanking duration for VCS(stop) | tBCS | 75 | 120 | 150 | ns | Guaranteed by design | 7 |
| Soft-start duration (option B) | tSSTART | 10 | 13 | ms | From 1st pulse to VCS = VILIM | 7 | |
| Frozen current setpoint (option H) | VI(freeze) | 250 | 300 | 350 | mV | 7 | |
| Over voltage protection threshold when DRV is low | VOVP(CS) | 1 | 1.05 | 1.1 | V | VCS going up | 7 |
| Blanking duration on OVP detection | tOVP,CS | 0.7 | 1 | 1.3 | µs | 7 | |
| Internal pull-up resistor | RFB(up) | 30 | 40 | 50 | kΩ | TJ = 25°C | 7 |
| Internal pull-up voltage on FB pin | VFB(ref) | 4.5 | 5 | 5.5 | V | 7 | |
| Feedback threshold for skip mode, going down | Vskip(in) | 0.9 | 1 | 1.1 | V | VFB going down, TJ = 25°C | 7 |
| Feedback threshold for skip mode, going up | Vskip(out) | 1.05 | 1.15 | 1.25 | V | VFB going up, TJ = 25°C | 7 |
| Skip out delay | tskip | 38 | µs | 7 | |||
| Voltage below which part enters off mode | VOFF | 0.5 | 0.6 | 0.7 | V | VCC > VCC(off) | 8 |
| Minimum hysteresis between VON and VOFF | VHYST | 500 | mV | VCC > VCC(off), VHV = 60 V | 8 | ||
| Go To Off mode timer | tGTOM | 400 | 500 | 600 | ms | VCC > VCC(off) | 8 |
| Fault timer duration | tfault | 108 | 128 | 178 | ms | 8 | |
| Fault timer reset time | tfault,res | 150 | 200 | 250 | µs | VCS < 0.7 V, D < 90% DMAX | 8 |
| Autorecovery mode latch-off time duration | tautorec | 0.85 | 1 | 1.35 | s | 8 | |
| Fault input high threshold | VOVP | 2.43 | 2.5 | 2.57 | V | VLatch going up | 8 |
| Fault input low threshold | VOTP | 0.38 | 0.4 | 0.42 | V | VLatch going down, TJ = 25°C | 8 |
| OTP resistance threshold | ROTP | 7.6 | 8 | 8.5 | kΩ | TJ = 25°C, external NTC resistance going down | 8 |
| Current source for direct NTC connection, normal operation | INTC | 47 | 50 | 53 | µA | VLatch = 0.2 V, TJ = 25°C | 8 |
| Blanking duration on high latch detection | tLatch(OVP) | 35 | 50 | 70 | µs | 8 | |
| Clamping voltage | Vclamp0(Latch) | 1 | 1.2 | 1.4 | V | ILatch = 0 mA | 8 |
| Clamping voltage | Vclamp1(Latch) | 1.8 | 2.4 | 3 | V | ILatch = 1 mA | 8 |
| Current flowing out of CS pin | IOPC(365) | 105 | 130 | 150 | µA | VHV = 365 V | 8 |
CAD (KiCad official)
- Symbol:
NCP12400BBHAA1DR2G - Footprint:
Package_SO:SOIC-8-N7_3.9x4.9mm_P1.27mm - 3D model: SOIC-7 (KiCad packages3D, STEP)
- 3D model files:
ncp12400bbhaa1dr2g-etched.step/ncp12400bbhaa1dr2g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ncp12400bbhaa1dr2g.step/ncp12400bbhaa1dr2g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (47 pp, sha256
5b6a98e6b6537aad, retrieved 2026-10-23, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).