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TM4C1237H6PZI

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Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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TM4C1237H6PZI

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)

TM4C1237H6PZI from Texas Instruments, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PD0 bidirectional GPIO port D bit 0, also ADC input AIN15, SSI1Clk/SSI3Clk, open-drain I2C3SCL, and WT2CCP0.
2 PD1 bidirectional GPIO port D bit 1, also ADC input AIN14, open-drain I2C3SDA, SSI1Fss/SSI3Fss, and WT2CCP1.
3 PD2 bidirectional GPIO port D bit 2, also ADC input AIN13, SSI1Rx/SSI3Rx, WT3CCP0, and USB0EPEN (output, Host mode power enable).
4 PD3 bidirectional GPIO port D bit 3, also ADC input AIN12, SSI1Tx/SSI3Tx, WT3CCP1, and USB0PFLT (input, Host mode power fault).
5 VDD power_in Positive supply for I/O and some logic.
6 GND power_in Ground reference for logic and I/O pins.
7 VDDA power_in Positive supply for the analog circuits (ADC, Analog Comparators, etc.), which must meet the voltage specification in Table 22-5 regardless of system implementation.
8 VREFA+ power_in ADC positive reference voltage, which sets the input voltage converted to full scale (4095); its limits are given in Table 22-33 and it is not 5-V tolerant.
9 VREFA- power_in ADC negative reference voltage, which sets the input voltage converted to 0; its limits are given in Table 22-33 and it is not 5-V tolerant.
10 GNDA power_in Ground reference for the analog circuits (ADC, Analog Comparators, etc.), kept separate from GND to limit digital noise on analog functions.
11 PJ2 bidirectional GPIO port J bit 2, also T2CCP0, and UART5 receive (U5Rx) alternate functions.
12 PE3 bidirectional GPIO port E bit 3, also ADC input AIN0 (not 5-V tolerant).
13 PE2 bidirectional GPIO port E bit 2, also ADC input AIN1 (not 5-V tolerant).
14 PE1 bidirectional GPIO port E bit 1, also ADC input AIN2 (not 5-V tolerant) and UART7 transmit (U7Tx).
15 PE0 bidirectional GPIO port E bit 0, also ADC input AIN3 (not 5-V tolerant) and UART7 receive (U7Rx).
16 PH0 bidirectional GPIO port H bit 0, also ADC input AIN16, SSI3Clk, and WT2CCP0.
17 PH1 bidirectional GPIO port H bit 1, also ADC input AIN17, SSI3Fss, and WT2CCP1.
18 PH2 bidirectional GPIO port H bit 2, also ADC input AIN18, SSI3Rx, and WT5CCP0.
19 PH3 bidirectional GPIO port H bit 3, also ADC input AIN19, SSI3Tx, and WT5CCP1.
20 VDD power_in Positive supply for I/O and some logic.
21 GND power_in Ground reference for logic and I/O pins.
22 PC7 bidirectional GPIO port C bit 7, also analog comparator 0 negative input C0- (5-V tolerant analog input), UART3 transmit, USB0PFLT, and WT1CCP1.
23 PC6 bidirectional GPIO port C bit 6, also analog comparator 0 positive input C0+, UART3 receive, USB0EPEN, and WT1CCP0.
24 PC5 bidirectional GPIO port C bit 5, also analog comparator 1 positive input C1+, UART1 CTS/Tx, UART4 Tx, and WT0CCP1.
25 PC4 bidirectional GPIO port C bit 4, also analog comparator 1 negative input C1-, UART1 RTS/Rx, UART4 Rx, and WT0CCP0.
26 PA0 bidirectional GPIO port A bit 0, default function UART0 receive (U0Rx).
27 PA1 bidirectional GPIO port A bit 1, default function UART0 transmit (U0Tx).
28 PA2 bidirectional GPIO port A bit 2, also SSI0 clock (SSI0Clk).
29 PA3 bidirectional GPIO port A bit 3, also SSI0 frame signal (SSI0Fss).
30 PA4 bidirectional GPIO port A bit 4, also SSI0 receive (SSI0Rx).
31 PA5 bidirectional GPIO port A bit 5, also SSI0 transmit (SSI0Tx).
32 VDD power_in Positive supply for I/O and some logic.
33 GND power_in Ground reference for logic and I/O pins.
34 PA6 bidirectional GPIO port A bit 6, also open-drain I2C1SCL (the port pin should not be configured as open drain for I2C clock use).
35 PA7 bidirectional GPIO port A bit 7, also open-drain I2C1SDA.
36 PF6 bidirectional GPIO port F bit 6, also open-drain I2C2SCL and T3CCP0.
37 PF5 bidirectional GPIO port F bit 5, also T2CCP1 and USB0PFLT (input, Host mode power fault).
38 VDDC power_in Core logic supply at 1.2 V from the on-chip LDO; VDDC pins should only be connected to each other and an external capacitor as specified in Table 22-12.
39 PF4 bidirectional GPIO port F bit 4, also T2CCP0, TRD3 trace output, U1DTR, and USB0EPEN.
40 PF0 bidirectional GPIO port F bit 0 (locked by default; commit control required for reprogramming), also NMI, analog comparator 0 output C0o, CAN0Rx, SSI1Rx, T0CCP0, TRD2, and U1RTS.
41 PF1 bidirectional GPIO port F bit 1, also analog comparator 1 output C1o, SSI1Tx, T0CCP1, TRD1, and U1CTS.
42 PF2 bidirectional GPIO port F bit 2, also analog comparator 2 output C2o, SSI1Clk, T1CCP0, TRD0, and U1DCD.
43 PF3 bidirectional GPIO port F bit 3, also CAN0Tx, SSI1Fss, T1CCP1, TRCLK trace clock, and U1DSR.
44 VDD power_in Positive supply for I/O and some logic.
45 GND power_in Ground reference for logic and I/O pins.
46 PK3 bidirectional GPIO port K bit 3, also SSI3 transmit (SSI3Tx).
47 PK2 bidirectional GPIO port K bit 2, also SSI3 receive (SSI3Rx).
48 PK1 bidirectional GPIO port K bit 1, also SSI3 frame signal (SSI3Fss).
49 PK0 bidirectional GPIO port K bit 0, also SSI3 clock (SSI3Clk).
50 WAKE input External input that brings the processor out of Hibernate mode when asserted (TTL levels).
51 HIB output Output that indicates the processor is in Hibernate mode (TTL levels).
52 XOSC0 input Hibernation module oscillator crystal input or external clock reference input for a 32.768-kHz crystal or oscillator.
53 GNDX power_in Ground for the Hibernation oscillator; connect to digital ground with the crystal load capacitors, or to digital ground when using an external oscillator.
54 XOSC1 output Hibernation module oscillator crystal output; leave unconnected when using a single-ended clock source.
55 VBAT power_in Power source for the Hibernation module, normally connected to the positive terminal of a battery as backup supply.
56 VDD power_in Positive supply for I/O and some logic.
57 GND power_in Ground reference for logic and I/O pins.
58 PF7 bidirectional GPIO port F bit 7, also open-drain I2C2SDA and T3CCP1.
59 PG3 bidirectional GPIO port G bit 3, also open-drain I2C4SDA and T5CCP1.
60 PG2 bidirectional GPIO port G bit 2, also open-drain I2C4SCL and T5CCP0.
61 PG1 bidirectional GPIO port G bit 1, also open-drain I2C3SDA and T4CCP1.
62 PG0 bidirectional GPIO port G bit 0, also open-drain I2C3SCL and T4CCP0.
63 RST input System reset input (TTL levels).
64 GND power_in Ground reference for logic and I/O pins.
65 OSC0 input Main oscillator crystal input or an external clock reference input (analog).
66 OSC1 output Main oscillator crystal output; leave unconnected when using a single-ended clock source.
67 VDD power_in Positive supply for I/O and some logic.
68 PJ0 bidirectional GPIO port J bit 0, not 5-V tolerant; also T1CCP0, UART4 receive (U4Rx), and USB0 D- differential data pin (USB0DM).
69 PJ1 bidirectional GPIO port J bit 1, not 5-V tolerant; also T1CCP1, UART4 transmit (U4Tx), and USB0 D+ differential data pin (USB0DP).
70 PB0 bidirectional GPIO port B bit 0, not 5-V tolerant; also T2CCP0, UART1 receive (U1Rx), and USB0ID (analog input sensing the USB ID state).
71 PB1 bidirectional GPIO port B bit 1, not 5-V tolerant; also T2CCP1, UART1 transmit (U1Tx), and USB0VBUS (analog I/O used in session request protocol).
72 PB2 bidirectional GPIO port B bit 2, also open-drain I2C0SCL and T3CCP0.
73 PB3 bidirectional GPIO port B bit 3, also open-drain I2C0SDA and T3CCP1.
74 PG4 bidirectional GPIO port G bit 4, also open-drain I2C1SCL, UART2 receive (U2Rx), USB0EPEN, and WT0CCP0.
75 PG5 bidirectional GPIO port G bit 5, also open-drain I2C1SDA, UART2 transmit (U2Tx), USB0PFLT, and WT0CCP1.
76 PH7 bidirectional GPIO port H bit 7, also SSI2 transmit (SSI2Tx) and WT4CCP1.
77 PH6 bidirectional GPIO port H bit 6, also SSI2 receive (SSI2Rx) and WT4CCP0.
78 PH5 bidirectional GPIO port H bit 5, also SSI2 frame signal (SSI2Fss) and WT3CCP1.
79 PH4 bidirectional GPIO port H bit 4, also SSI2 clock (SSI2Clk) and WT3CCP0.
80 VDD power_in Positive supply for I/O and some logic.
81 GND power_in Ground reference for logic and I/O pins.
82 PC3 bidirectional GPIO port C bit 3, default JTAG/SWD function (TDO and SWO output), also T5CCP1.
83 PC2 bidirectional GPIO port C bit 2, default JTAG TDI input, also T5CCP0.
84 PC1 bidirectional GPIO port C bit 1, default JTAG TMS/SWDIO function, also T4CCP1.
85 PC0 bidirectional GPIO port C bit 0, default JTAG/SWD clock (TCK/SWCLK) function, also T4CCP0.
86 VDDC power_in Core logic supply at 1.2 V from the on-chip LDO; VDDC pins should only be connected to each other and an external capacitor as specified in Table 22-12.
87 PG6 bidirectional GPIO port G bit 6, also analog comparator 2 positive input C2+ (5-V tolerant), open-drain I2C5SCL, and WT1CCP0.
88 PG7 bidirectional GPIO port G bit 7, also analog comparator 2 negative input C2- (5-V tolerant), open-drain I2C5SDA, and WT1CCP1.
89 PE6 bidirectional GPIO port E bit 6, also ADC input AIN21 (not 5-V tolerant).
90 PE7 bidirectional GPIO port E bit 7, also ADC input AIN20 (not 5-V tolerant) and UART1 Ring Indicator (U1RI).
91 PB5 bidirectional GPIO port B bit 5, also ADC input AIN11 (not 5-V tolerant), CAN0Tx, SSI2Fss, and T1CCP1.
92 PB4 bidirectional GPIO port B bit 4, also ADC input AIN10 (not 5-V tolerant), CAN0Rx, SSI2Clk, and T1CCP0.
93 VDD power_in Positive supply for I/O and some logic.
94 GND power_in Ground reference for logic and I/O pins.
95 PE4 bidirectional GPIO port E bit 4, also ADC input AIN9 (not 5-V tolerant), CAN0Rx, open-drain I2C2SCL, and UART5 receive (U5Rx).
96 PE5 bidirectional GPIO port E bit 5, also ADC input AIN8 (not 5-V tolerant), CAN0Tx, open-drain I2C2SDA, and UART5 transmit (U5Tx).
97 PD4 bidirectional GPIO port D bit 4, also ADC input AIN7 (not 5-V tolerant), UART6 receive (U6Rx), and WT4CCP0.
98 PD5 bidirectional GPIO port D bit 5, also ADC input AIN6 (not 5-V tolerant), UART6 transmit (U6Tx), and WT4CCP1.
99 PD6 bidirectional GPIO port D bit 6, also ADC input AIN5 (not 5-V tolerant), UART2 receive (U2Rx), and WT5CCP0.
100 PD7 bidirectional GPIO port D bit 7, also ADC input AIN4 (not 5-V tolerant), NMI (non-maskable interrupt), UART2 transmit (U2Tx), and WT5CCP1; locked by default and requires commit control to reprogram.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package LQFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

CAD (KiCad official)

  • Symbol: TM4C1237H6PZI
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: tm4c1237h6pzi-etched.step / tm4c1237h6pzi-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tm4c1237h6pzi.step / tm4c1237h6pzi.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (1310 pp, sha256 3db610f4ef4d92dd, retrieved 2026-10-11, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF