AD5271BRMZ-100 from Analog Devices, in a MSOP-10. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VDD	power_in	Positive power supply, which must be decoupled with 0.1 µF ceramic and 10 µF capacitors; the part operates from 2.7 V to 5.5 V single-supply or ±2.5 V to ±2.75 V dual-supply.
2	A	passive	Terminal A of the RDAC, with VSS ≤ VA ≤ VDD and a maximum continuous current of ±3 mA for the RAW = 20 kΩ option (±2 mA for 50 kΩ and 100 kΩ).
3	W	passive	Wiper terminal of the RDAC, with VSS ≤ VW ≤ VDD.
4	VSS	power_in	Negative supply, connected to 0 V for single-supply applications and decoupled with 0.1 µF ceramic and 10 µF capacitors.
5	EXT_CAP	passive	External capacitor pin; a 1 µF capacitor with a voltage rating of ≥7 V must be connected between EXT_CAP and VSS.
6	GND	power_in	Ground pin serving as the logic ground reference, to which the digital control inputs are referenced.
7	SDO	output	Serial data output for daisy-chain or readback mode; it is an open-drain output that requires an external pull-up resistor even if not used.
8	DIN	input	Serial data input that clocks data into the 16-bit input register together with SCLK.
9	SCLK	input	Serial clock input; data is clocked into the shift register on the falling edge, at rates up to 50 MHz.
10	SYNC	input	Active-low frame synchronization input that enables the shift register when taken low; the selected register updates on the rising edge following the 16th clock, and a rising edge before the 16th clock cancels the write.

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	MSOP-10
Category	ADC/DAC/Data Conversion
Pins	10

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Resistor Integral Nonlinearity	R-INL	-1		1	LSB		3
Resistor Differential Nonlinearity	R-DNL	-1		1	LSB		5
Nominal Resistor Tolerance, R-Perf Mode		-1	0.5	1	%	See Table 5 and Table 6	5
Nominal Resistor Tolerance, Normal Mode		-15		15	%		5
Wiper Resistance			35	70	Ω	Code = zero scale	5
Common-Mode Leakage Current				50	nA	VA = VW	5
Input Logic High	VINH	2			V		5
Input Logic Low	VINL			0.8	V		5
Input Current	IIN	-1		1	µA		5
Output Voltage Low	VOL			0.4	V	VDD = 2.7 V to 5.5 V, VSS = 0 V; RPULL_UP = 2.2 kΩ to VDD	5
Output Voltage Low	VOL			0.6	V	VDD = 2.5 V to 2.75 V, VSS = −2.5 V to −2.75 V; RPULL_UP = 2.2 kΩ to VDD	5
Tristate Leakage Current		-1		1	µA		5
Single-Supply Power Range	VDD	2.7		5.5	V	VSS = 0 V	5
Dual-Supply Power Range	VDD/VSS	2.5		2.75	V		5
Positive Supply Current	IDD			1	µA		5
Negative Supply Current	ISS			-1	µA		5
50-TP Store Current, Positive	IDD_OTP_STORE			4	mA		5
50-TP Store Current, Negative	ISS_OTP_STORE			-4	mA		5
OTP Read Current, Positive	IDD_OTP_READ			500	µA		5
OTP Read Current, Negative	ISS_OTP_READ			-500	µA		5
Power Dissipation				5.5	µW	VIH = VDD or VIL = GND	5
Interface timing: SCLK cycle time	t1	20			ns		6
Interface timing: SCLK high time	t2	10			ns		6
Interface timing: SCLK low time	t3	10			ns		6
Interface timing: SYNC to SCLK falling edge setup time	t4	15			ns		6
Interface timing: Data setup time	t5	5			ns		6
Interface timing: Data hold time	t6	5			ns		6
Interface timing: SCLK falling edge to SYNC rising edge	t7	1			ns		6
Interface timing: Minimum SYNC high time	t8	500			ns		6
Interface timing: SYNC rising edge to next SCLK fall ignored	t9	15			ns		6
Interface timing: SCLK rising edge to SDO valid	t10			450	ns	RPULL_UP = 2.2 kΩ to VDD with a capacitance load of 168 pF	6
RDAC register write command execute time, R-Perf	tRDAC_R-PERF			2	µs		6
RDAC register write command execute time, normal	tRDAC_NORMAL			600	ns		6
Memory readback execute time	tMEMORY_READ			6	µs		6
Memory program time	tMEMORY_PROGRAM			350	ms		6
Reset 50-TP restore time	tRESET			0.6	ms		6
Power-on 50-TP restore time	tPOWER-UP			2	ms	Maximum time after VDD − VSS is equal to 2.5 V	6
VDD to GND	VDD	-0.3		7	V		8
VSS to GND	VSS	-7		0.3	V		8
VDD to VSS	VDD-VSS			7	V		8
EXT_CAP to VSS	EXT_CAP			7	V		8
Continuous current IA, IW	IA, IW	-2		2	mA	RAW = 50 kΩ, 100 kΩ	8
Operating Temperature Range	TA	-40		125	°C	Includes programming of 50-TP memory	8
Maximum Junction Temperature	TJ			150	°C		8
Storage Temperature Range		-65		150	°C		8
Reflow Soldering Peak Temperature				260	°C	Time at peak temperature 20 sec to 40 sec	8
Nominal resistance between Terminal A and Terminal W	RWA		100		kΩ		21
Resistance Temperature Coefficient			5		ppm/°C	Code = full scale	5
Thermal resistance junction to ambient, 10-Lead MSOP	θJA		161.8		°C/W	JEDEC natural convection	8
Thermal resistance junction to board, 10-Lead MSOP	θJB		25.2		°C/W	JEDEC θJB environment	8

CAD (KiCad official)

Symbol: AD5271BRMZ-100
Footprint: Package_SO:MSOP-10_3x3mm_P0.5mm
3D model: MSOP-10 (KiCad packages3D, STEP)
3D model files: ad5271brmz-100-etched.step / ad5271brmz-100-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad5271brmz-100.step / ad5271brmz-100.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (24 pp, sha256 7856686a104180a6, retrieved 2026-10-30, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

AD5271BRMZ-100

Verified AD5271BRMZ-100

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

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