component
UC2572DTR
Public Made by Adomby adom
Texas Instruments DC-DC Converters, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownUC2572DTR
Texas Instruments · DC-DC Converters · SOIC-8
UC2572DTR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | EAINV | input | Inverting input to the error amplifier and summing junction for 3VREF and VOUT sense; the non-inverting input is internally tied to GND and the pin sources a maximum of 1mA. |
| 2 | EAOUT | output | Error amplifier output, used with EAINV for loop compensation components. |
| 3 | CS | input | Current limit sense pin connected to a ground-referenced sense resistor in series with the flyback inductor; OUT is held high (PMOS off) if CS exceeds 0.2V. |
| 4 | VCC | power_in | Input supply voltage to the chip, range 4.75 to 30V, bypass with a 1µF capacitor. |
| 5 | OUT | output | Gate drive for the external PMOS switch connected between VCC and the flyback inductor, swinging between VCC and GND. |
| 6 | GND | power_in | Circuit ground. |
| 7 | RAMP | passive | Oscillator and PWM ramp, frequency set by a capacitor to GND with F = 1/(15k·CRAMP), recommended range 10kHz to 200kHz. |
| 8 | 3VREF | power_out | Precision 3V reference output, bypass with a 100nF capacitor to GND. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage (absolute maximum) | VCC | 35 | V | 2 | |||
| Error amp input voltage (absolute maximum) | EAINV | -0.6 | V | 2 | |||
| Error amp output current (absolute maximum) | IEAOUT | 25 | mA | 2 | |||
| RAMP pin voltage (absolute maximum) | RAMP | -0.3 | 4 | V | 2 | ||
| CS pin voltage (absolute maximum) | CS | -0.3 | V | 2 | |||
| Output current (absolute maximum) | Iout | -0.7 | 0.7 | A | 2 | ||
| 3VREF output current (absolute maximum) | I3VREF | -15 | mA | 2 | |||
| Storage temperature (absolute maximum) | -65 | 150 | °C | 2 | |||
| Junction temperature (absolute maximum) | -65 | 150 | °C | 2 | |||
| Lead temperature (absolute maximum) | 300 | °C | Soldering, 10 sec. | 2 | |||
| Supply voltage VCC (recommended) | VCC | 4.75 | 30 | V | Input voltage supply range (pin description) | 4 | |
| Recommended oscillator frequency range | 10 | 200 | kHz | Set by CRAMP on RAMP pin | 4 | ||
| Operating temperature range (UC2572, D package) | -40 | 85 | °C | UC2572 grade, D package | 2 | ||
| 3VREF reference voltage | 3VREF | 2.94 | 3 | 3.06 | V | 2 | |
| Reference line regulation | 1 | 10 | mV | VCC = 4.75 to 30V | 2 | ||
| Reference load regulation | 1 | 10 | mV | I3VREF = 0V to –5mA | 2 | ||
| Oscillator frequency | 85 | 100 | 115 | kHz | VCC = 5V to 30V | 2 | |
| Error amp input offset (EAINV) | EAINV | -10 | 0 | 10 | mV | EAOUT = 2V | 2 |
| Error amp row IEANV (parameter name not printed) | IEANV | -0.2 | -0.9 | V | IEANV = –1mA | 2 | |
| Error amp input bias row IEAINV | IEAINV | -0.2 | -1 | A | EAOUT = 2V | 2 | |
| Error amp open-loop voltage gain (AVOL) | AVOL | 65 | 90 | dB | EAOUT = 0.5V to 3V | 2 | |
| EAOUT high | 3.6 | 4 | 4.4 | V | EAINV = –100mV | 2 | |
| EAOUT low | 0.1 | 0.2 | V | EAINV = 100mV | 2 | ||
| EAOUT sink current | IEAOUT | -350 | -500 | µA | EAINV = –100mV, EAOUT = 2V | 2 | |
| EAOUT source current | IEAOUT | 7 | 20 | mA | EAINV = 100mV, EAOUT = 2V | 2 | |
| Error amp unity gain bandwidth | 0.6 | 1 | MHz | TJ = 25°C, F = 10kHz | 2 | ||
| Current sense comparator threshold | 0.185 | 0.205 | 0.225 | V | 2 | ||
| CS input bias current | -0.4 | -1 | µA | CS = 0 | 2 | ||
| CS propagation delay | 300 | nS | 2 | ||||
| OUT high saturation | 0 | 0.3 | V | IOUT = 0 | 3 | ||
| OUT high saturation | 0.7 | 1.5 | V | IOUT = –10mA | 3 | ||
| OUT high saturation | 1.5 | 2.5 | V | IOUT = –100mA | 3 | ||
| OUT low saturation | 0.1 | 0.4 | V | IOUT = 10mA | 3 | ||
| OUT low saturation | 1.5 | 2.2 | V | IOUT = 100mA | 3 | ||
| OUT rise time | 30 | 80 | nS | TJ = 25°C, CLOAD = 1nF + 3.3 Ohms | 3 | ||
| OUT fall time | 30 | 80 | nS | TJ = 25°C, CLOAD = 1nF + 3.3 Ohms | 3 | ||
| Maximum duty cycle | 92 | 96 | % | EAINV = +100mV, VCC = 5V to 30V | 3 | ||
| Minimum duty cycle | 0 | % | EAINV = –100mV, VCC = 5V to 30V | 3 | |||
| Modulator gain | 45 | 55 | 65 | %/V | EAOUT = 1.5V to 2.5V | 3 | |
| UVLO start threshold | 3.5 | 4.2 | 4.5 | V | 3 | ||
| UVLO hysteresis | 100 | 200 | 300 | mV | 3 | ||
| Sleep mode threshold | 1.8 | 2.2 | 2.6 | V | 3 | ||
| Supply current (operating) | IVCC | 9 | 15 | mA | VCC = 5V, 30V | 3 | |
| Supply current (sleep mode) | 50 | 150 | A | VCC = 30, CS = 3V | 3 |
CAD (KiCad official)
- Symbol:
UC2572DTR - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
uc2572dtr-etched.step/uc2572dtr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);uc2572dtr.step/uc2572dtr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (10 pp, sha256
9d4bf256c535d704, retrieved 2026-10-11, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).