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CD74AC109M96

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Texas Instruments Flip Flops, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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CD74AC109M96

Texas Instruments · Flip Flops · SOIC-16

CD74AC109M96 from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1CLR input Active-low clear input of flip-flop 1; a low level resets the outputs regardless of the other inputs.
2 1J input J data input of flip-flop 1, transferred to the outputs on the positive clock edge when PRE and CLR are high.
3 1K input K data input of flip-flop 1, transferred to the outputs on the positive clock edge when PRE and CLR are high.
4 1CLK input Positive-edge-triggered clock input of flip-flop 1.
5 1PRE input Active-low preset input of flip-flop 1; a low level sets the outputs regardless of the other inputs.
6 1Q output True output of flip-flop 1 with ±24-mA drive at VCC = 4.5 V to 5.5 V.
7 ~{1Q} output Complementary output of flip-flop 1 with ±24-mA drive at VCC = 4.5 V to 5.5 V.
8 GND power_in Ground; continuous current through VCC or GND is limited to ±100 mA.
9 ~{2Q} output Complementary output of flip-flop 2 with ±24-mA drive at VCC = 4.5 V to 5.5 V.
10 2Q output True output of flip-flop 2 with ±24-mA drive at VCC = 4.5 V to 5.5 V.
11 2PRE input Active-low preset input of flip-flop 2; a low level sets the outputs regardless of the other inputs.
12 2CLK input Positive-edge-triggered clock input of flip-flop 2.
13 2K input K data input of flip-flop 2, transferred to the outputs on the positive clock edge when PRE and CLR are high.
14 2J input J data input of flip-flop 2, transferred to the outputs on the positive clock edge when PRE and CLR are high.
15 2CLR input Active-low clear input of flip-flop 2; a low level resets the outputs regardless of the other inputs.
16 VCC power_in Supply voltage, 1.5 V to 5.5 V recommended operating range (absolute maximum −0.5 V to 6 V).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16
Category Logic ICs
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 1.5 5.5 V TA = -55°C to 125°C 3
Operating free-air temperature range TA -55 125 °C CD74AC109M96 catalog ordering range 1
High-level input voltage VIH 1.2 V VCC = 1.5 V, TA = -55°C to 125°C 3
High-level input voltage VIH 2.1 V VCC = 3 V, TA = -55°C to 125°C 3
High-level input voltage VIH 3.85 V VCC = 5.5 V, TA = -55°C to 125°C 3
Low-level input voltage VIL 0.3 V VCC = 1.5 V, TA = -55°C to 125°C 3
Low-level input voltage VIL 0.9 V VCC = 3 V, TA = -55°C to 125°C 3
Low-level input voltage VIL 1.65 V VCC = 5.5 V, TA = -55°C to 125°C 3
High-level output current IOH -24 mA VCC = 4.5 V to 5.5 V, TA = -55°C to 125°C 3
Low-level output current IOL 24 mA VCC = 4.5 V to 5.5 V, TA = -55°C to 125°C 3
Input transition rise or fall rate ∆t/∆v 50 ns/V VCC = 1.5 V to 3 V 3
Input transition rise or fall rate ∆t/∆v 20 ns/V VCC = 3.6 V to 5.5 V 3
Supply voltage range VCC -0.5 6 V 3
Input clamp current IIK -20 20 mA VI < 0 V or VI > VCC 3
Output clamp current IOK -50 50 mA VO < 0 V or VO > VCC 3
Continuous output current IO -50 50 mA VO > 0 V or VO < VCC 3
Continuous current through VCC or GND -100 100 mA 3
Storage temperature range Tstg -65 150 °C 3
Package thermal impedance (M package, SOIC) θJA 73 °C/W M package, calculated per JESD 51-7 3
High-level output voltage VOH 1.4 V VI = VIH or VIL; IOH = -50 µA; VCC = 1.5 V; TA = -55°C to 125°C 4
High-level output voltage VOH 2.9 V VI = VIH or VIL; IOH = -50 µA; VCC = 3 V; TA = -55°C to 125°C 4
High-level output voltage VOH 4.4 V VI = VIH or VIL; IOH = -50 µA; VCC = 4.5 V; TA = -55°C to 125°C 4
High-level output voltage VOH 2.4 V VI = VIH or VIL; IOH = -4 mA; VCC = 3 V; TA = -55°C to 125°C 4
High-level output voltage VOH 3.7 V VI = VIH or VIL; IOH = -24 mA; VCC = 4.5 V; TA = -55°C to 125°C 4
Low-level output voltage VOL 0.1 V VI = VIH or VIL; IOL = 50 µA; VCC = 1.5 V; TA = -55°C to 125°C 4
Low-level output voltage VOL 0.5 V VI = VIH or VIL; IOL = 12 mA; VCC = 3 V; TA = -55°C to 125°C 4
Input current II -1 1 µA VI = VCC or GND; VCC = 5.5 V; TA = -55°C to 125°C 4
Supply current ICC 80 µA VI = VCC or GND; IO = 0; VCC = 5.5 V; TA = -55°C to 125°C 4
Input capacitance Ci 10 pF 4
Clock frequency fclock 8 MHz VCC = 1.5 V; TA = -55°C to 125°C 4
Pulse duration CLK high or low t 63 ns VCC = 1.5 V; TA = -55°C to 125°C 4
Pulse duration CLR or PRE low tw 56 ns VCC = 1.5 V; TA = -55°C to 125°C 4
Setup time, before CLK↑ J or K tsu 69 ns VCC = 1.5 V; TA = -55°C to 125°C 4
Recovery time, before CLK↑ CLR↑ or PRE↑ trec 31 ns VCC = 1.5 V; TA = -55°C to 125°C 4
Clock frequency fclock 71 MHz VCC = 3.3 V ± 0.3 V; TA = -55°C to 125°C 5
Pulse duration CLK high or low t 7 ns VCC = 3.3 V ± 0.3 V; TA = -55°C to 125°C 5
Pulse duration CLR or PRE tw 6.3 ns VCC = 3.3 V ± 0.3 V; TA = -55°C to 125°C 5
Setup time, before CLK↑ J or K tsu 7.7 ns VCC = 3.3 V ± 0.3 V; TA = -55°C to 125°C 5
Recovery time, before CLK↑ CLR↑ or PRE↑ trec 3.5 ns VCC = 3.3 V ± 0.3 V; TA = -55°C to 125°C 5
Clock frequency fclock 100 MHz VCC = 5 V ± 0.5 V; TA = -55°C to 125°C 5
Pulse duration CLK high or low t 5 ns VCC = 5 V ± 0.5 V; TA = -55°C to 125°C 5
Pulse duration CLR or PRE tw 4.5 ns VCC = 5 V ± 0.5 V; TA = -55°C to 125°C 5
Setup time, before CLK↑ J or K tsu 5.5 ns VCC = 5 V ± 0.5 V; TA = -55°C to 125°C 5
Recovery time, before CLK↑ CLR↑ or PRE↑ trec 2.5 ns VCC = 5 V ± 0.5 V; TA = -55°C to 125°C 5
Propagation delay CLK to Q or Q̅ (tPLH) tPLH 129 ns VCC = 1.5 V, CL = 50 pF; TA = -55°C to 125°C 5
Propagation delay CLR or PRE to Q or Q̅ (tPLH) tPLH 153 ns VCC = 1.5 V, CL = 50 pF; TA = -55°C to 125°C 5
Propagation delay CLK to Q or Q̅ (tPHL) tPHL 129 ns VCC = 1.5 V, CL = 50 pF; TA = -55°C to 125°C 5
Propagation delay CLR or PRE to Q or Q̅ (tPHL) tPHL 153 ns VCC = 1.5 V, CL = 50 pF; TA = -55°C to 125°C 5
Propagation delay CLK to Q or Q̅ (tPLH) tPLH 3.6 14.4 ns VCC = 3.3 V ± 0.3 V, CL = 50 pF; TA = -55°C to 125°C 5
Propagation delay CLR or PRE to Q or Q̅ (tPLH) tPLH 4.3 17.1 ns VCC = 3.3 V ± 0.3 V, CL = 50 pF; TA = -55°C to 125°C 5
Propagation delay CLK to Q or Q̅ (tPHL) tPHL 3.6 14.4 ns VCC = 3.3 V ± 0.3 V, CL = 50 pF; TA = -55°C to 125°C 5
Propagation delay CLR or PRE to Q or Q̅ (tPHL) tPHL 4.3 17.1 ns VCC = 3.3 V ± 0.3 V, CL = 50 pF; TA = -55°C to 125°C 5

CAD (KiCad official)

  • Symbol: CD74AC109M96
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: cd74ac109m96-etched.step / cd74ac109m96-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd74ac109m96.step / cd74ac109m96.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (17 pp, sha256 0795bdeab05c3875, retrieved 2026-10-18, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF