component

SN74LVTH573DWR

Public Made by Adom

by adom

Texas Instruments Latches, SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogicsn74lvth573dwrfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads on click. Unloads only if this page sits in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads on click. Unloads only if this page sits in the background.

PCB Footprint

Open full view ↗
Loads on click. Unloads only if this page sits in the background.

Datasheet

Open in new tab ↗
Loads on click. Unloads only if this page sits in the background.
Download PDF
Contents

README

markdown

SN74LVTH573DWR

Texas Instruments · Latches · SOIC-20-300mil

SN74LVTH573DWR from Texas Instruments, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE input Buffered active-low output enable: when high it forces the eight Q outputs into the high-impedance state without affecting the latch contents, and it should be tied to VCC through a pullup resistor to keep the outputs high-Z during power up and power down.
2 1D input Data input to transparent latch 1; bus-hold circuitry holds a floating input at a valid logic level, and the recommended input voltage is up to 5.5 V.
3 2D input Data input to transparent latch 2; bus-hold circuitry holds a floating input at a valid logic level, and the recommended input voltage is up to 5.5 V.
4 3D input Data input to transparent latch 3; bus-hold circuitry holds a floating input at a valid logic level, and the recommended input voltage is up to 5.5 V.
5 4D input Data input to transparent latch 4; bus-hold circuitry holds a floating input at a valid logic level, and the recommended input voltage is up to 5.5 V.
6 5D input Data input to transparent latch 5; bus-hold circuitry holds a floating input at a valid logic level, and the recommended input voltage is up to 5.5 V.
7 6D input Data input to transparent latch 6; bus-hold circuitry holds a floating input at a valid logic level, and the recommended input voltage is up to 5.5 V.
8 7D input Data input to transparent latch 7; bus-hold circuitry holds a floating input at a valid logic level, and the recommended input voltage is up to 5.5 V.
9 8D input Data input to transparent latch 8; bus-hold circuitry holds a floating input at a valid logic level, and the recommended input voltage is up to 5.5 V.
10 GND power_in Ground reference for the device.
11 LE input Latch enable: while high the Q outputs follow the D inputs, and when taken low the Q outputs latch the data present at D; LE high pulse duration must be at least 3 ns, with data setup of 0.7 ns (3.3 V) and hold of 1.5 ns before and after LE falls.
12 8Q tri_state Three-state output of latch 8; drives up to IOL 64 mA low and IOH −32 mA high (SN74LVTH573 recommended levels) and goes high-impedance when OE is high.
13 7Q tri_state Three-state output of latch 7; drives up to IOL 64 mA low and IOH −32 mA high (SN74LVTH573 recommended levels) and goes high-impedance when OE is high.
14 6Q tri_state Three-state output of latch 6; drives up to IOL 64 mA low and IOH −32 mA high (SN74LVTH573 recommended levels) and goes high-impedance when OE is high.
15 5Q tri_state Three-state output of latch 5; drives up to IOL 64 mA low and IOH −32 mA high (SN74LVTH573 recommended levels) and goes high-impedance when OE is high.
16 4Q tri_state Three-state output of latch 4; drives up to IOL 64 mA low and IOH −32 mA high (SN74LVTH573 recommended levels) and goes high-impedance when OE is high.
17 3Q tri_state Three-state output of latch 3; drives up to IOL 64 mA low and IOH −32 mA high (SN74LVTH573 recommended levels) and goes high-impedance when OE is high.
18 2Q tri_state Three-state output of latch 2; drives up to IOL 64 mA low and IOH −32 mA high (SN74LVTH573 recommended levels) and goes high-impedance when OE is high.
19 1Q tri_state Three-state output of latch 1; drives up to IOL 64 mA low and IOH −32 mA high (SN74LVTH573 recommended levels) and goes high-impedance when OE is high.
20 VCC power_in Supply voltage, specified from 2.7 V to 3.6 V for the SN74LVTH573.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-20-300mil
Category Logic
Pins 20

CAD (KiCad official)

  • Symbol: SN74LVTH573DWR
  • Footprint: Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm
  • 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
  • 3D model files: sn74lvth573dwr-etched.step / sn74lvth573dwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74lvth573dwr.step / sn74lvth573dwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (28 pp, sha256 3cfdfbaf569799e7, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF