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MSP430FR5889IPMR
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), QFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMSP430FR5889IPMR
Texas Instruments · Microcontrollers (MCU/MPU/SOC) · QFP-64(10x10)
MSP430FR5889IPMR from Texas Instruments, in a QFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P4.3 | bidirectional | General-purpose digital I/O; USCI_A0 slave out/master in (SPI) or receive data (UART); USCI_B1 slave transmit enable (SPI) |
| 2 | P1.4 | bidirectional | General-purpose digital I/O; USCI_B0 clock (SPI slave/master); USCI_A0 slave transmit enable (SPI); Timer_A1 CCR0 capture/compare output |
| 3 | P1.5 | bidirectional | General-purpose digital I/O; USCI_B0 slave transmit enable (SPI); USCI_A0 clock (SPI slave/master); Timer_A0 CCR0 capture/compare output |
| 4 | P1.6 | bidirectional | General-purpose digital I/O; USCI_B0 slave in/master out (SPI) or I2C data; BSL data (I2C BSL); Timer_A0 CCR1 capture/compare output |
| 5 | P1.7 | bidirectional | General-purpose digital I/O; USCI_B0 slave out/master in (SPI) or I2C clock; BSL clock (I2C BSL); Timer_A0 CCR2 capture/compare output |
| 6 | P2.4 | bidirectional | General-purpose digital I/O; Timer_B0 CCR3 capture/compare output |
| 7 | P2.5 | bidirectional | General-purpose digital I/O; Timer_B0 CCR4 capture/compare output |
| 8 | P2.6 | bidirectional | General-purpose digital I/O; Timer_B0 CCR5 capture/compare output; ESI Comparator 1 output |
| 9 | P2.7 | bidirectional | General-purpose digital I/O; Timer_B0 CCR6 capture/compare output; ESI Comparator 2 output |
| 10 | P5.0 | bidirectional | General-purpose digital I/O; Timer_A1 CCR1 capture/compare output; MCLK master clock output |
| 11 | P5.1 | bidirectional | General-purpose digital I/O; Timer_A1 CCR2 capture/compare output |
| 12 | P5.2 | bidirectional | General-purpose digital I/O; Timer_A1 CCR0 capture/compare; Timer_A1 clock input; ACLK auxiliary clock output |
| 13 | P5.3 | bidirectional | General-purpose digital I/O; USCI_B1 slave transmit enable (SPI) |
| 14 | P3.0 | bidirectional | General-purpose digital I/O; USCI_B1 clock signal input (SPI slave) or output (SPI master) |
| 15 | P3.1 | bidirectional | General-purpose digital I/O; USCI_B1 slave in/master out (SPI) or I2C data |
| 16 | P3.2 | bidirectional | General-purpose digital I/O; USCI_B1 slave out/master in (SPI) or I2C clock |
| 17 | DVSS1 | power_in | Digital ground supply return path for power distribution network |
| 18 | DVCC1 | power_in | Digital power supply input; recommend 1µF plus 100nF low-ESR decoupling capacitor |
| 19 | TEST | input | Test mode pin for digital I/O selection on JTAG pins; Spy-Bi-Wire input clock |
| 20 | RST/NMI | bidirectional | Reset input active low; Nonmaskable interrupt input; Spy-Bi-Wire data input/output; requires 47kΩ pull-up or internal pullup with 2.2nF pulldown |
| 21 | PJ.0 | bidirectional | General-purpose digital I/O; JTAG test data output; Timer_B0 high-impedance output control; SMCLK output; CPU status register SCG1 debug |
| 22 | PJ.1 | bidirectional | General-purpose digital I/O; JTAG test data input or test clock; MCLK output; CPU status register SCG0 debug |
| 23 | PJ.2 | bidirectional | General-purpose digital I/O; JTAG test mode select; ACLK output; CPU status register OSCOFF debug |
| 24 | PJ.3 | bidirectional | General-purpose digital I/O; JTAG test clock; Comparator output; CPU status register CPUOFF debug |
| 25 | P3.3 | bidirectional | General-purpose digital I/O; Timer_A1 CCR1 capture/compare output; Timer_B0 clock input |
| 26 | P3.4 | bidirectional | General-purpose digital I/O; USCI_A1 slave in/master out (SPI) or transmit data (UART); Timer_B0 CCR0 capture/compare output |
| 27 | P3.5 | bidirectional | General-purpose digital I/O; USCI_A1 slave out/master in (SPI) or receive data (UART); Timer_B0 CCR1 capture/compare output |
| 28 | P3.6 | bidirectional | General-purpose digital I/O; USCI_A1 clock input (SPI slave) or output (SPI master); Timer_B0 CCR2 capture/compare output |
| 29 | P3.7 | bidirectional | General-purpose digital I/O; USCI_A1 slave transmit enable (SPI); Timer_B0 CCR3 capture/compare output |
| 30 | P2.3 | bidirectional | General-purpose digital I/O; USCI_A0 slave transmit enable (SPI); Timer_B0 high-impedance output control |
| 31 | P2.2 | bidirectional | General-purpose digital I/O; USCI_A0 clock (SPI slave/master); Timer_B0 CCR4 capture/compare output; RTC clock calibration output |
| 32 | P2.1 | bidirectional | General-purpose digital I/O; USCI_A0 slave out/master in (SPI) or receive data (UART); Timer_B0 CCR5 capture/compare; DMA external trigger |
| 33 | P2.0 | bidirectional | General-purpose digital I/O; USCI_A0 slave in/master out (SPI) or transmit data (UART); Timer_B0 CCR6 capture/compare; Timer_B0 clock input |
| 34 | DVSS2 | power_in | Digital ground supply return path for power distribution network |
| 35 | DVCC2 | power_in | Digital power supply input; recommend 1µF plus 100nF low-ESR decoupling capacitor |
| 36 | P1.3 | bidirectional | General-purpose digital I/O; ESI test signal 4; Timer_A1 CCR2 capture/compare; Analog input A3; Comparator input C3 |
| 37 | P1.2 | bidirectional | General-purpose digital I/O; Timer_A1 CCR1 capture/compare; Timer_A0 clock input; Comparator output; Analog input A2; Comparator input C2 |
| 38 | P1.1 | bidirectional | General-purpose digital I/O; Timer_A0 CCR2 capture/compare; Timer_A1 clock input; Comparator output; Analog input A1/VREF+ output/VeREF+ input |
| 39 | P1.0 | bidirectional | General-purpose digital I/O; Timer_A0 CCR1 capture/compare; DMA external trigger; RTC calibration output; Analog input A0/VREF- output/VeREF- input |
| 40 | P9.0 | bidirectional | General-purpose digital I/O; ESI channel 0 sensor excitation output and signal input; ESI test signal 0; Analog input A8; Comparator input C8 |
| 41 | P9.1 | bidirectional | General-purpose digital I/O; ESI channel 1 sensor excitation output and signal input; ESI test signal 1; Analog input A9; Comparator input C9 |
| 42 | P9.2 | bidirectional | General-purpose digital I/O; ESI channel 2 sensor excitation output and signal input; ESI test signal 2; Analog input A10; Comparator input C10 |
| 43 | P9.3 | bidirectional | General-purpose digital I/O; ESI channel 3 sensor excitation output and signal input; ESI test signal 3; Analog input A11; Comparator input C11 |
| 44 | P9.4 | bidirectional | General-purpose digital I/O; ESI channel 0 signal input to comparator; Analog input A12; Comparator input C12 |
| 45 | P9.5 | bidirectional | General-purpose digital I/O; ESI channel 1 signal input to comparator; Analog input A13; Comparator input C13 |
| 46 | P9.6 | bidirectional | General-purpose digital I/O; ESI channel 2 signal input to comparator; Analog input A14; Comparator input C14 |
| 47 | P9.7 | bidirectional | General-purpose digital I/O; ESI channel 3 signal input to comparator; Analog input A15; Comparator input C15 |
| 48 | ESIDVCC | power_in | Extended Scan Interface power supply input; recommend 1µF plus 100nF low-ESR decoupling capacitor |
| 49 | ESIDVSS | power_in | Extended Scan Interface ground supply return path for power distribution network |
| 50 | ESICI | input | Extended Scan Interface Scan IF input to Comparator module for sensor interface |
| 51 | ESICOM | passive | Extended Scan Interface common termination point for Scan IF sensors; leave open if not used |
| 52 | AVCC1 | power_in | Analog power supply input; recommend 1µF plus 100nF low-ESR decoupling capacitor |
| 53 | AVSS3 | power_in | Analog ground supply return path for power distribution network |
| 54 | PJ.7 | bidirectional | General-purpose digital I/O; high-frequency crystal oscillator XT2 output terminal (HFXOUT) |
| 55 | PJ.6 | bidirectional | General-purpose digital I/O; high-frequency crystal oscillator XT2 input terminal (HFXIN) |
| 56 | AVSS1 | power_in | Analog ground supply return path for power distribution network |
| 57 | PJ.4 | bidirectional | General-purpose digital I/O; low-frequency crystal oscillator XT1 input terminal (LFXIN) |
| 58 | PJ.5 | bidirectional | General-purpose digital I/O; low-frequency crystal oscillator XT1 output terminal (LFXOUT) |
| 59 | AVSS2 | power_in | Analog ground supply return path for power distribution network |
| 60 | P4.0 | bidirectional | General-purpose digital I/O; USCI_B1 slave in/master out (SPI) or I2C data; MCLK master clock output |
| 61 | P4.1 | bidirectional | General-purpose digital I/O; USCI_B1 slave out/master in (SPI) or I2C clock; ACLK auxiliary clock output |
| 62 | DVSS3 | power_in | Digital ground supply return path for power distribution network |
| 63 | DVCC3 | power_in | Digital power supply input; recommend 1µF plus 100nF low-ESR decoupling capacitor |
| 64 | P4.2 | bidirectional | General-purpose digital I/O; USCI_A0 slave in/master out (SPI) or transmit data (UART); USCI_B1 clock (SPI slave/master) |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | QFP-64(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 64 |
CAD (KiCad official)
- Symbol:
MSP430FR5889IPMR - Footprint:
Package_QFP:TQFP-64_10x10mm_P0.5mm - 3D model: QFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files:
msp430fr5889ipmr-etched.step/msp430fr5889ipmr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);msp430fr5889ipmr.step/msp430fr5889ipmr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (189 pp, sha256
b0919e7a6373e8f8, retrieved 2026-09-26, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-4-6(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).