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Contents

Pinout
Key specifications
Electrical characteristics
CAD (KiCad official)
Provenance

README

markdown

STM8L152R6T6

STMicroelectronics · ST Microelectronics · LQFP-64(10x10)

STM8L152R6T6 from STMicroelectronics, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	PA0	bidirectional	Port A0 high-sink I/O (input pull-up during and after reset) with alternate functions [USART1_CK], SWIM input/output, BEEP output and IR_TIM output; high sink LED driver capability.
2	NRST/PA1	bidirectional	Reset input with pull-up at power-up (30-60 kOhm), usable only as push-pull output PA1 when configured as GPIO.
3	PA2	bidirectional	Port A2 high-sink I/O with HSE oscillator input OSC_IN and remap options [USART1_TX]/[SPI1_MISO].
4	PA3	bidirectional	Port A3 high-sink I/O with HSE oscillator output OSC_OUT and remap options [USART1_RX]/[SPI1_MOSI].
5	PA4	bidirectional	Port A4 five-volt-tolerant I/O with TIM2_BKIN/[TIM2_ETR], LCD_COM0, ADC1_IN2 and [COMP1_INP].
6	PA5	bidirectional	Port A5 five-volt-tolerant I/O with TIM3_BKIN/[TIM3_ETR], LCD_COM1, ADC1_IN1 and [COMP1_INP].
7	PA6	bidirectional	Port A6 five-volt-tolerant I/O with ADC1_TRIG, LCD_COM2, ADC1_IN0 and [COMP1_INP].
8	PA7	bidirectional	Port A7 five-volt-tolerant I/O with LCD_SEG0 and TIM5_CH1.
9	VSSA/VREF-	power_in	Analog ground and ADC1 negative voltage reference.
10	VSS1	power_in	I/O ground.
11	VDD1	power_in	Digital power supply, 1.65 to 3.6 V, must not be left unconnected.
12	VDDA	power_in	Analog supply voltage, 1.65 to 3.6 V (minimum 1.8 V when ADC1 is used), to be connected to VDD.
13	VREF+	power_in	Positive voltage reference for ADC1 and DAC1/2 (VREF+_DAC), provided externally.
14	PG0	bidirectional	Port G0 five-volt-tolerant I/O with LCD_SEG28, USART3_RX and [TIM2_BKIN].
15	PG1	bidirectional	Port G1 five-volt-tolerant I/O with LCD_SEG29, USART3_TX and [TIM3_BKIN].
16	PG2	bidirectional	Port G2 five-volt-tolerant I/O with LCD_SEG30 and USART3_CK.
17	PG3	bidirectional	Port G3 five-volt-tolerant I/O with LCD_SEG31 and [TIM3_ETR].
18	VLCD	passive	LCD booster external capacitor pin (STM8L152 only; reserved and tied to VDD on STM8L151).
19	PE0	bidirectional	Port E0 five-volt-tolerant I/O with LCD_SEG1 and TIM5_CH2.
20	PE1	bidirectional	Port E1 five-volt-tolerant I/O with TIM1_CH2N and LCD_SEG2.
21	PE2	bidirectional	Port E2 five-volt-tolerant I/O with TIM1_CH3N, LCD_SEG3 and [CCO].
22	PE3	bidirectional	Port E3 five-volt-tolerant I/O with LCD_SEG4 and USART2_RX.
23	PE4	bidirectional	Port E4 five-volt-tolerant I/O with LCD_SEG5, DAC_TRIG2 and USART2_TX.
24	PE5	bidirectional	Port E5 five-volt-tolerant I/O with LCD_SEG6, ADC1_IN23, [COMP1_INP]/[COMP2_INP] and USART2_CK.
25	PD0	bidirectional	Port D0 five-volt-tolerant I/O with TIM3_CH2, [ADC1_TRIG], LCD_SEG7, ADC1_IN22 and [COMP2_INP].
26	PD1	bidirectional	Port D1 five-volt-tolerant I/O with TIM3_ETR, LCD_COM3, ADC1_IN21 and [COMP1_INP]/[COMP2_INP].
27	PD2	bidirectional	Port D2 five-volt-tolerant I/O with TIM1_CH1, LCD_SEG8, ADC1_IN20 and [COMP1_INP].
28	PD3	bidirectional	Port D3 five-volt-tolerant I/O with TIM1_ETR, LCD_SEG9, ADC1_IN19 and [COMP1_INP].
29	VDD3	power_in	I/O supply voltage, 1.65 to 3.6 V, must not be left unconnected.
30	VSS3	power_in	I/O ground voltage.
31	PB0	bidirectional	Port B0 five-volt-tolerant I/O (pull-up during reset) with TIM2_CH1, LCD_SEG10, ADC1_IN18 and [COMP1_INP].
32	PB1	bidirectional	Port B1 five-volt-tolerant I/O with TIM3_CH1, LCD_SEG11, ADC1_IN17 and [COMP1_INP].
33	PB2	bidirectional	Port B2 five-volt-tolerant I/O with TIM2_CH2, LCD_SEG12, ADC1_IN16 and [COMP1_INP].
34	PB3	bidirectional	Port B3 five-volt-tolerant I/O with TIM2_ETR, LCD_SEG13, ADC1_IN15 and [COMP1_INP].
35	PB4	bidirectional	Port B4 five-volt-tolerant I/O (pull-up during reset) with SPI1_NSS, LCD_SEG14, ADC1_IN14 and [COMP1_INP].
36	PB5	bidirectional	Port B5 five-volt-tolerant I/O with SPI1_SCK, LCD_SEG15, ADC1_IN13 and [COMP1_INP].
37	PB6	bidirectional	Port B6 five-volt-tolerant I/O with SPI1_MOSI, LCD_SEG16, ADC1_IN12 and [COMP1_INP].
38	PB7	bidirectional	Port B7 five-volt-tolerant I/O with SPI1_MISO, LCD_SEG17, ADC1_IN11 and [COMP1_INP].
39	PF0	bidirectional	Port F0 I/O with ADC1_IN24, DAC_OUT1 and [USART3_TX].
40	PF1	bidirectional	Port F1 I/O with ADC1_IN25, DAC channel 2 output and [USART3_RX].
41	PF4	bidirectional	Port F4 five-volt-tolerant I/O with LCD_SEG36 and [LCD_COM4].
42	PF5	bidirectional	Port F5 five-volt-tolerant I/O with LCD_SEG37 and [LCD_COM5].
43	PF6	bidirectional	Port F6 five-volt-tolerant I/O with LCD_SEG38 and [LCD_COM6].
44	PF7	bidirectional	Port F7 five-volt-tolerant I/O with LCD_SEG39 and [LCD_COM7].
45	PD4	bidirectional	Port D4 five-volt-tolerant I/O with TIM1_CH2, LCD_SEG18, ADC1_IN10 and [COMP1_INP].
46	PD5	bidirectional	Port D5 five-volt-tolerant I/O with TIM1_CH3, LCD_SEG19, ADC1_IN9 and [COMP1_INP].
47	PD6	bidirectional	Port D6 five-volt-tolerant I/O with TIM1_BKIN, LCD_SEG20, ADC1_IN8, RTC_CALIB, [COMP1_INP] and VREFINT output.
48	PD7	bidirectional	Port D7 five-volt-tolerant I/O with TIM1_CH1N, LCD_SEG21, ADC1_IN7, RTC_ALARM, [COMP1_INP] and VREFINT output.
49	PG4	bidirectional	Port G4 five-volt-tolerant I/O with LCD_SEG32 and SPI2_NSS.
50	PG5	bidirectional	Port G5 five-volt-tolerant I/O with LCD_SEG33 and SPI2_SCK.
51	PG6	bidirectional	Port G6 five-volt-tolerant I/O with LCD_SEG34 and SPI2_MOSI.
52	PG7	bidirectional	Port G7 five-volt-tolerant I/O with LCD_SEG35 and SPI2_MISO.
53	PC0	bidirectional	Port C0 five-volt-tolerant true open-drain I/O with I2C1_SDA.
54	PC1	bidirectional	Port C1 five-volt-tolerant true open-drain I/O with I2C1_SCL.
55	VDD2	power_in	I/O supply voltage, 1.65 to 3.6 V, must not be left unconnected.
56	VSS2	power_in	I/O ground voltage.
57	PC2	bidirectional	Port C2 five-volt-tolerant I/O with USART1_RX, LCD_SEG22, ADC1_IN6, [COMP1_INP] and VREFINT output.
58	PC3	bidirectional	Port C3 five-volt-tolerant I/O with USART1_TX, LCD_SEG23, ADC1_IN5, [COMP2_INM] and [COMP1_INP].
59	PC4	bidirectional	Port C4 five-volt-tolerant I/O with USART1_CK, I2C1_SMB, [CCO], LCD_SEG24, ADC1_IN4, [COMP2_INM] and [COMP1_INP].
60	PC5	bidirectional	Port C5 five-volt-tolerant I/O with LSE oscillator input OSC32_IN and remap options [SPI1_NSS]/[USART1_TX].
61	PC6	bidirectional	Port C6 five-volt-tolerant I/O with LSE oscillator output OSC32_OUT and remap options [SPI1_SCK]/[USART1_RX].
62	PC7	bidirectional	Port C7 five-volt-tolerant I/O with LCD_SEG25, ADC1_IN3, [COMP2_INM] and [COMP1_INP].
63	PE6	bidirectional	Port E6 five-volt-tolerant I/O with LCD_SEG26, PVD_IN and TIM5_BKIN.
64	PE7	bidirectional	Port E7 five-volt-tolerant I/O with LCD segment 27 (printed LED_SEG27) and TIM5_ETR.

Key specifications

Parameter	Value
Manufacturer	STMicroelectronics
Package	LQFP-64(10x10)
Category	Embedded Processors & Controllers
Pins	64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
External supply voltage (including VDDA)	VDD - VSS	-0.3		4	V		69
Input voltage on true open-drain pins (PC0, PC1)	VIN			4	V	VDD + 4.0 max as printed; VSS - 0.3 min	69
Total current into VDD power line (source)	IVDD			80	mA		70
Total current out of VSS ground line (sink)	IVSS			80	mA		70
Output current sunk by IR_TIM pin	IIO			80	mA	with high sink LED driver capability	70
Output current sunk by any other I/O and control pin	IIO			25	mA		70
Output current sourced by any I/O and control pin	IIO	-25			mA		70
Injected current on any other pin	IINJ(PIN)	-5		5	mA		70
Injected current on FT pins	IINJ(PIN)	-5		0	mA		70
Total injected current (sum of all I/O and control pins)	ΣIINJ(PIN)	-25		25	mA		70
Storage temperature range	TSTG	-65		150	°C		70
Maximum junction temperature	TJ			150	°C		70
System clock frequency	fSYSCLK	0		16	MHz	1.65 V ≤ VDD < 3.6 V	71
Standard operating voltage, BOR disabled	VDD	1.65		3.6	V	BOR detector disabled (D suffix version)	71
Standard operating voltage, BOR enabled	VDD	1.8		3.6	V	BOR detector enabled	71
Analog operating voltage, ADC and DAC not used	VDDA	1.65		3.6	V	ADC and DAC not used	71
Analog operating voltage, ADC or DAC used	VDDA	1.8		3.6	V	ADC or DAC used	71
Power dissipation LQFP64	PD			416	mW	TA = 85 °C for suffix 6 devices	71
Temperature range	TA	-40		85	°C	1.65 V ≤ VDD < 3.6 V (6 suffix version)	71
Junction temperature range	TJ	-40		105	°C	-40 °C ≤ TA < 85 °C (6 suffix version)	71
Power-on reset threshold	VPOR	1.3	1.5	1.65	V	Rising edge	72
Power-down reset threshold	VPDR	1.3	1.5	1.65	V	Falling edge	72
Brown-out reset threshold 0	VBOR0	1.67	1.7	1.74	V	BOR_TH[2:0]=000, falling edge	72
Brown-out reset threshold 1	VBOR1	1.87	1.93	1.97	V	BOR_TH[2:0]=001, falling edge	72
Brown-out reset threshold 2	VBOR2	2.22	2.3	2.35	V	BOR_TH[2:0]=010, falling edge	72
Brown-out reset threshold 3	VBOR3	2.45	2.55	2.6	V	BOR_TH[2:0]=011, falling edge	72
Brown-out reset threshold 4	VBOR4	2.68	2.8	2.85	V	BOR_TH[2:0]=100, falling edge	72
PVD threshold 0	VPVD0	1.8	1.84	1.88	V	Falling edge	73
PVD threshold 6	VPVD6	2.97	3.05	3.09	V	Falling edge	73
Supply current in run mode, code from RAM, HSI	IDD(RUN)		1.62	1.79	mA	HSI RC osc. (16 MHz), fCPU = 16 MHz, all peripherals OFF, max at 85 °C	75
Supply current in run mode, code from Flash, HSI	IDD(RUN)		3.54	3.67	mA	HSI RC osc., fCPU = 16 MHz, all peripherals OFF, max at 85 °C	76
HSI frequency	fHSI		16		MHz	VDD = 3.0 V	93
HSI accuracy, factory calibrated	ACCHSI	-1		1	%	VDD = 3.0 V, TA = 25 °C	93
HSI accuracy, factory calibrated	ACCHSI	-2.5		2	%	VDD = 3.0 V, -10 °C ≤TA ≤ 85 °C	93
HSI accuracy, factory calibrated	ACCHSI	-4.5		3	%	1.65 V ≤ VDD ≤ 3.6 V, -40 °C ≤TA ≤ 125 °C	93
LSI frequency	fLSI	26	38	56	kHz	VDD = 1.65 V to 3.6 V, TA = -40 to 125 °C	94
HSE external clock source frequency	fHSE_ext	1		16	MHz		90
HSE oscillator frequency	fHSE	1		16	MHz		91
Flash operating voltage	VDD	1.65		3.6	V	all modes, read/write/erase, fSYSCLK = 16 MHz	96
Data retention (program memory)	tRET	30			years	after 10000 erase/write cycles at TA=-40 to +85 °C (6 suffix), TRET=+85 °C	96
Erase/write cycles (program memory)	NRW	10			kcycles	TA=-40 to +85 °C (6 suffix)	96
Erase/write cycles (data memory)	NRW	300			kcycles	TA=-40 to +85 °C (6 suffix)	96
Input high level voltage on FT pins	VIH			5.5	V	Input voltage on five-volt tolerant (FT) pins with VDD ≥ 2 V	98
Schmitt trigger voltage hysteresis, standard I/Os	Vhys		200		mV	Standard I/Os	98
Input leakage current, standard I/Os	Ilkg			50	nA	VSS≤VIN≤ VDD, Standard I/Os	98
Weak pull-up equivalent resistor	RPU	30	45	60	kΩ	VIN=VSS	98
Output low level voltage (high sink ports)	VOL			0.45	V	IIO = +2 mA, VDD = 3.0 V	101
Output low level voltage (high sink ports)	VOL			0.7	V	IIO = +10 mA, VDD = 3.0 V	101
NRST input low level voltage	VIL(NRST)			0.8	V		103
NRST input high level voltage	VIH(NRST)	1.4			V		103
NRST pull-up equivalent resistor	RPU(NRST)	30	45	60	kΩ		103
Reference voltage output	VREFINT out	1.202	1.224	1.242	V		111
Temperature sensor reference voltage at 90°C	V90	0.58	0.597	0.614	V	90°C ±5 °C	112

CAD (KiCad official)

Symbol: STM8L152R6T6
Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
3D model files: stm8l152r6t6-etched.step / stm8l152r6t6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm8l152r6t6.step / stm8l152r6t6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: STMicroelectronics datasheet (147 pp, sha256 193f2133f3d81d2b, retrieved 2026-10-22, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF