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TLE9842QX
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Infineon Microcontrollers (MCU/MPU/SOC), VQFN-48-EP(7x7). Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
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PCB Footprint
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Datasheet
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README
markdownTLE9842QX
Infineon · Microcontrollers (MCU/MPU/SOC) · VQFN-48-EP(7x7)
TLE9842QX from Infineon, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | LIN | bidirectional | LIN 2.2 bus interface input/output. Single-wire local interconnect network line with integrated transceiver; pull-up enabled after reset. |
| 2 | GNDLIN | power_in | LIN transceiver ground reference. |
| 3 | HS1 | output | High-Side Switch output 1 (min. 150 mA). Drives LEDs, switch panels, or supplies for cyclic-sense; PWM capable. |
| 4 | N.U. | unconnected | Not Used. See datasheet Chapter 27.2 for handling of N.U. pins. |
| 5 | MON1 | input | High-Voltage Monitor Input 1. Wake source with programmable threshold; can be routed to ADC for analog measurement. |
| 6 | MON2 | input | High-Voltage Monitor Input 2. Wake source with programmable threshold; can be routed to ADC for analog measurement. |
| 7 | MON3 | input | High-Voltage Monitor Input 3. Wake source with programmable threshold; can be routed to ADC for analog measurement. |
| 8 | MON4 | input | High-Voltage Monitor Input 4. Wake source with programmable threshold; can be routed to ADC for analog measurement. |
| 9 | N.U. | unconnected | Not Used. See datasheet Chapter 27.2 for handling of N.U. pins. |
| 10 | N.C. | unconnected | Not connected; can be tied to GND. |
| 11 | LS1 | output | Low-Side Switch output 1. Open-drain low-side driver for relays or inductive loads; PWM capable. |
| 12 | LS2 | output | Low-Side Switch output 2. Open-drain low-side driver for relays or inductive loads; PWM capable. |
| 13 | GNDLS | power_in | Low-side switch ground return (LS1, LS2). |
| 14 | P1.0 | bidirectional | Port 1 bit 0 general-purpose I/O. Reset state input; alternate functions per Table 9. |
| 15 | P1.1 | bidirectional | Port 1 bit 1 general-purpose I/O. Reset state input; alternate functions per Table 9. |
| 16 | P1.2 | bidirectional | Port 1 bit 2 general-purpose I/O. Reset state input; alternate functions per Table 9. |
| 17 | P0.1 | bidirectional | Port 0 bit 1 general-purpose I/O. Reset state input with pull-up; alternate functions per Table 8. |
| 18 | TMS/SWD_IO | bidirectional | Test-mode select input / Serial Wire Debug data I/O. Reset state input with pull-down. |
| 19 | GNDP | power_in | Core / port supply ground. |
| 20 | P0.0/SWD_CLK | bidirectional | Port 0 bit 0 general-purpose I/O / Serial Wire Debug clock. Reset state input with pull-up; alternate functions per Table 8. |
| 21 | RESET | bidirectional | Bidirectional reset input/output with internal pull-up. Not available during Sleep Mode. |
| 22 | P0.2 | bidirectional | Port 0 bit 2 general-purpose I/O. Reset state input with pull-down; alternate functions per Table 8. See Chapter 27.4 for SWD debug mode connection. |
| 23 | P0.3 | bidirectional | Port 0 bit 3 general-purpose I/O. Reset state input with pull-up; alternate functions per Table 8. |
| 24 | P0.4 | bidirectional | Port 0 bit 4 general-purpose I/O. Reset state input with pull-up; alternate functions per Table 8. |
| 25 | P0.5 | bidirectional | Port 0 bit 5 general-purpose I/O. Reset state input with pull-up; alternate functions per Table 8. |
| 26 | P1.4 | bidirectional | Port 1 bit 4 general-purpose I/O. Reset state input; alternate functions per Table 9. |
| 27 | N.C. | unconnected | Not connected; can be tied to GND. |
| 28 | N.C. | unconnected | Not connected; can be tied to GND. |
| 29 | N.C. | unconnected | Not connected; can be tied to GND. |
| 30 | GNDP | power_in | Core / port supply ground (second GNDP pin). |
| 31 | P2.5/XTAL2 | bidirectional | Port 2 bit 5 input / external oscillator output XTAL2. XTAL2 drives the crystal in External Crystal Mode; configurable by user. |
| 32 | P2.4/XTAL1 | input | Port 2 bit 4 input / external oscillator input XTAL1. Accepts external clock or crystal drive; configurable by user. |
| 33 | P2.2/AN2 | input | Port 2 bit 2 input / ADC1 analog input channel 8 (AN2). Input-only port; alternate functions per Table 10. |
| 34 | P2.6/AN6 | input | Port 2 bit 6 input / ADC1 analog input channel 10 (AN6). Input-only port; alternate functions per Table 10. |
| 35 | P2.7/AN7 | input | Port 2 bit 7 input / ADC1 analog input channel 11 (AN7). Input-only port; alternate functions per Table 10. |
| 36 | P2.3/AN3 | input | Port 2 bit 3 input / ADC1 analog input channel 9 (AN3). Input-only port; alternate functions per Table 10. |
| 37 | P2.1/AN1 | input | Port 2 bit 1 input / ADC1 analog input channel 7 (AN1). Input-only port; alternate functions per Table 10. |
| 38 | N.C. | unconnected | Not connected; can be tied to GND. |
| 39 | P2.0/AN0 | input | Port 2 bit 0 input / ADC1 analog input channel 12 (AN0). Input-only port; alternate functions per Table 10. |
| 40 | N.C. | unconnected | Not connected; can be tied to GND. |
| 41 | N.C. | unconnected | Not connected; can be tied to GND. |
| 42 | VDDC | power_out | 1.5 V core LDO output (0.9 V in Stop Mode). Requires an external buffer/bypass capacitor; do not connect external loads. |
| 43 | GNDA | power_in | Analog supply ground. |
| 44 | VDDP | power_out | 5.0 V I/O port LDO output. Requires an external buffer/bypass capacitor; do not connect external loads. |
| 45 | VDDEXT | power_out | External 5.0 V voltage regulator output, up to 20 mA. Supplies external sensors or logic (e.g. Hall sensors). |
| 46 | N.C. | unconnected | Not connected; can be tied to GND. |
| 47 | VS | power_in | Battery supply input. 3.0 V to 28 V functional range; feeds the internal PMU regulators. |
| 48 | VBAT_SENSE | input | Battery supply voltage sense input. Routed to the ADC/measurement unit for battery voltage monitoring. |
| EP | EP | power_in | Exposed thermal pad on the package underside. Must be connected to GND for thermal and electrical performance. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Infineon |
| Package | VQFN-48-EP(7x7) |
| Category | MCU |
| Pins | 49 |
Ordering variants
Same part, different packaging or reel option.
TLE9842QX
CAD (KiCad official)
- Symbol:
TLE9842QX - Footprint:
Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm - 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Infineon datasheet (128 pp, sha256
717ed197f78e830b, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).