CT415-HSN850MR from Allegro MicroSystems, LLC, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	IP+	passive	Input primary conductor (positive) carrying the current to be measured through the integrated current carrying conductor.
2	IP+	passive	Input primary conductor (positive) carrying the current to be measured through the integrated current carrying conductor.
3	IP-	passive	Output primary conductor (negative) as printed in the terminal list.
4	IP-	passive	Output primary conductor (negative) as printed in the terminal list.
5	GND	power_in	Ground.
6	FILTER	passive	Filter pin to improve noise performance by connecting an external capacitor to set the cutoff frequency; no connect if the FILTER pin is not used.
7	OUT	output	Analog output voltage that represents the measured current.
8	VCC	power_in	Supply voltage.

Key specifications

Parameter	Value
Manufacturer	Allegro MicroSystems, LLC
Package	SOIC-8
Category	Magnetic Sensors
Pins	8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply Voltage Strength	VCC	-0.3		6	V		3
Analog Input/Output Pins Maximum Voltage	VI/O	-0.3			V	Max = VCC + 0.3 V, lower of that or 6.0 V	3
Current Carrying Conductor Maximum Current	ICCC(MAX)			70	A	TA = 25°C	3
Dielectric Surge Strength Test Voltage	VSURGE	6			kV	IEC 61000-4-5, ±5 pulses at 2/60 s, 1.2 µs rise, 50 µs width	3
Surge Strength Test Current	ISURGE	3			kA	±5 pulses at 3/60 s, 8.0 µs rise, 20 µs width	3
Electrostatic Discharge Protection Level (HBM)		-2		2	kV	HBM per JESD22-A114	3
Electrostatic Discharge Protection Level (CDM)		-0.5		0.5	kV	CDM per JESD22-C101	3
Junction Temperature	TJ	-40		150	°C		3
Storage Temperature	TSTG	-65		155	°C		3
Lead Soldering Temperature	TL			260	°C	10 seconds	3
Supply Voltage Range	VCC	4.75	5	5.5	V		3
Output Voltage Range	VOUT	0			V	Max = VCC	3
Output Current	IOUT	-1		1	mA		3
Operating Ambient Temperature (Extended Industrial)	TA	-40	25	125	°C	Extended Industrial	3
Operating Ambient Temperature (Automotive)	TA	-40	25	125	°C	Automotive	3
Supply Current	ICC		6	9	mA	fBW = 1 MHz, no load, IP = 0 A	6
OUT Maximum Drive Capability	IOUT	-1		1	mA	OUT covers 10% to 90% of VCC span	6
OUT Capacitive Load	CL_OUT			100	pF		6
OUT Voltage Linear Range, Typical	VOUT	0.5		4.5	V	VSIG_AC = ±2.00 V, VSIG_DC = +4.00 V	6
Power-On Time	tON		100	200	µs	VCC ≥ 2.50 V	6
Current Range (minimum)	IRANGE	-50		50	A		15
Voltage Output Quiescent	VOQ	2.495	2.5	2.505	V	TA = 25°C, IP = 0 A	15
Total Output Error	ETOT	-3		3	% FS	IP sweep from IP(MIN) to IP(MAX)	15
Linearity Error	ELIN	-0.3		0.3	% FS	IP = IP(MAX), TA = -40°C to 125°C	15
Sensitivity Error	ESENS	-2.5		2.5	%	IP = IP(MAX), TA = 125°C	15
Sensitivity Error	ESENS	-2.4		2.4	%	IP = IP(MAX), TA = -40°C	15
Offset Voltage Error	VOE	-6		6	mV	IP = 0 A, TA = 25°C	15
Offset Voltage Error	VOE	-33		33	mV	IP = 0 A, TA = 125°C	15
Offset Voltage Error	VOE	-30		30	mV	IP = 0 A, TA = -40°C	15
Total Error Including Lifetime Drift	ETOT(DRIFT)	-2.3		2.3	% FS	IP = IP(MAX), TA = -40°C to 125°C	15
Sensitivity Error Including Lifetime Drift	ESENS(DRIFT)	-3.1		3.1	%	IP = IP(MAX), TA = -40°C to 125°C	15
Offset Voltage Error Including Lifetime Drift	VOE(DRIFT)	-41		41	mV	IP = 0 A, TA = -40°C to 125°C	15
Sensitivity	S		40		mV/A	IRANGE(MIN) < IP < IRANGE(MAX)	15
Bandwidth	fBW		1		MHz	Small Signal = -3 dB	15
Noise	eN		14		mARMS	TA = 25°C, fBW = 100 kHz	15
OUT Resistive Load	RL_OUT		100		kΩ		6
Internal Filter Resistance	RFILTER		15		kΩ		6
Primary Conductor Resistance	RIP		1		mΩ		6
Power Supply Rejection Ratio	PSRR		35		dB		6
Sensitivity Power Supply Rejection Ratio	SPSRR		35		dB		6
Offset Power Supply Rejection Ratio	OPSRR		40		dB		6
Common Mode Field Rejection Ratio	CMFRR		-40		dB		6
Rise Time	tRISE		200		ns	IP = IRANGE(MAX), TA = 25°C, CL = 220 pF	6
Response Time	tRESPONSE		300		ns	IP = IRANGE(MAX), TA = 25°C, CL = 220 pF	6
Propagation Delay	tDELAY		250		ns	IP = IRANGE(MAX), TA = 25°C, CL = 220 pF	6
Undervoltage Lockout Rising	VUVLO		2.5		V	Rising VDD	6
Undervoltage Lockout Falling	VUVLO		2.45		V	Falling VDD	6
UVLO Hysteresis	VUV_HYS		50		mV		6

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
contacts	copper		CCC pins be connected to as much copper area as possible. It is	21

CAD (KiCad official)

Symbol: CT415-HSN850MR
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOIC-8 (KiCad packages3D, STEP)
3D model files: ct415-hsn850mr-etched.step / ct415-hsn850mr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ct415-hsn850mr.step / ct415-hsn850mr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Allegro MicroSystems, LLC datasheet (26 pp, sha256 8a1d9d9957705ebd, retrieved 2026-11-02, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

CT415-HSN850MR

Verified CT415-HSN850MR

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

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