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MC74VHCT50ADR2G

Public Made by Adom

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onsemi Buffers, Drivers, Receivers, Transceivers, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Datasheet

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Contents

README

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MC74VHCT50ADR2G

onsemi · Buffers, Drivers, Receivers, Transceivers · SOIC-14

MC74VHCT50ADR2G from onsemi, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A1 input Data input of buffer 1; TTL-compatible thresholds (VIL max 0.8 V and VIH min 2.0 V at VCC 4.5 V to 5.5 V) and it tolerates input voltages up to 7 V regardless of the supply voltage.
2 Y1 output Noninverting buffer 1 output with a full 5 V CMOS level swing; the output structure is protected when VCC = 0 V.
3 A2 input Data input of buffer 2; TTL-compatible thresholds (VIL max 0.8 V and VIH min 2.0 V at VCC 4.5 V to 5.5 V) and it tolerates input voltages up to 7 V regardless of the supply voltage.
4 Y2 output Noninverting buffer 2 output with a full 5 V CMOS level swing; the output structure is protected when VCC = 0 V.
5 A3 input Data input of buffer 3; TTL-compatible thresholds (VIL max 0.8 V and VIH min 2.0 V at VCC 4.5 V to 5.5 V) and it tolerates input voltages up to 7 V regardless of the supply voltage.
6 Y3 output Noninverting buffer 3 output with a full 5 V CMOS level swing; the output structure is protected when VCC = 0 V.
7 GND power_in Ground reference for the device.
8 Y4 output Noninverting buffer 4 output with a full 5 V CMOS level swing; the output structure is protected when VCC = 0 V.
9 A4 input Data input of buffer 4; TTL-compatible thresholds (VIL max 0.8 V and VIH min 2.0 V at VCC 4.5 V to 5.5 V) and it tolerates input voltages up to 7 V regardless of the supply voltage.
10 Y5 output Noninverting buffer 5 output with a full 5 V CMOS level swing; the output structure is protected when VCC = 0 V.
11 A5 input Data input of buffer 5; TTL-compatible thresholds (VIL max 0.8 V and VIH min 2.0 V at VCC 4.5 V to 5.5 V) and it tolerates input voltages up to 7 V regardless of the supply voltage.
12 Y6 output Noninverting buffer 6 output with a full 5 V CMOS level swing; the output structure is protected when VCC = 0 V.
13 A6 input Data input of buffer 6; TTL-compatible thresholds (VIL max 0.8 V and VIH min 2.0 V at VCC 4.5 V to 5.5 V) and it tolerates input voltages up to 7 V regardless of the supply voltage.
14 VCC power_in Positive supply; recommended DC supply range is 2.0 V to 5.5 V.

Key specifications

Parameter Value
Manufacturer onsemi
Package SOIC-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
DC Supply Voltage VCC -0.5 7 V 2
DC Input Voltage VIN -0.5 7 V 2
DC Output Voltage VOUT -0.5 7 V Output in HIGH or LOW State 2
DC Input Diode Current IIK 20 mA 2
DC Output Diode Current IOK 20 mA 2
DC Output Source/Sink Current IO 25 mA 2
DC Supply Current per Supply Pin ICC 50 mA 2
DC Ground Current per Ground Pin IGND 50 mA 2
Storage Temperature Range TSTG -65 150 C 2
Lead Temperature TL 260 C 1 mm from Case for 10 Seconds 2
Junction Temperature under Bias TJ 150 C 2
Thermal Resistance Junction-to-Ambient θJA 125 C/W SOIC; minimum pad spacing on FR4 board (Note 1) 2
Power Dissipation in Still Air PD 500 mW SOIC; still air 2
ESD Withstand Voltage Human Body Model VESD 2000 V Human Body Model (Note 2); printed as > 2000 2
ESD Withstand Voltage Machine Model VESD 200 V Machine Model (Note 3); printed as > 200 2
ESD Withstand Voltage Charged Device Model VESD 2000 V Charged Device Model (Note 4) 2
Latch-Up Performance ILatch-Up 300 mA Above VCC and below GND at 85C (Note 5) 2
DC Supply Voltage VCC 2 5.5 V 2
DC Input Voltage VIN 0 5.5 V 2
DC Output Voltage VOUT 0 5.5 V VCC = 0 2
DC Output Voltage VOUT 0 V High or Low State 2
Operating Temperature Range TA -55 125 C 2
Input Rise and Fall Time tr, tf 0 100 ns/V VCC = 3.3 V ± 0.3 V 2
Input Rise and Fall Time tr, tf 0 20 ns/V VCC = 5.0 V ± 0.5 V 2
Minimum High-Level Input Voltage VIH 1.2 V VCC = 3.0 V; TA ≤ 125°C 3
Minimum High-Level Input Voltage VIH 2 V VCC = 4.5 V; TA ≤ 125°C 3
Maximum Low-Level Input Voltage VIL 0.53 V VCC = 3.0 V; TA ≤ 125°C 3
Maximum Low-Level Input Voltage VIL 0.8 V VCC = 4.5 V; TA ≤ 125°C 3
Minimum High-Level Output Voltage VOH 2.9 V VIN = VIH or VIL; IOH = −50 μA; VCC = 3.0 V; TA ≤ 125°C 3
Minimum High-Level Output Voltage VOH 4.4 V VIN = VIH or VIL; IOH = −50 μA; VCC = 4.5 V; TA ≤ 125°C 3
Minimum High-Level Output Voltage VOH 2.34 V VIN = VIH or VIL; IOH = −4 mA; VCC = 3.0 V; TA ≤ 125°C 3
Minimum High-Level Output Voltage VOH 3.66 V VIN = VIH or VIL; IOH = −8 mA; VCC = 4.5 V; TA ≤ 125°C 3
Maximum Low-Level Output Voltage VOL 0.1 V VIN = VIH or VIL; IOL = 50 μA; VCC = 3.0 V; TA ≤ 125°C 3
Maximum Low-Level Output Voltage VOL 0.52 V VIN = VIH or VIL; IOH = −4 mA; IOL = 8 mA; VCC = 3.0 V; TA ≤ 125°C 3
Maximum Input Leakage Current IIN -1 1 μA VIN = 5.5 V or GND; VCC = 0 to 5.5 V; TA ≤ 125°C 3
Maximum Quiescent Supply Current ICC 2 μA VIN = VCC or GND; VCC = 5.5 V; TA = 25°C 3
Maximum Quiescent Supply Current ICC 20 μA VIN = VCC or GND; VCC = 5.5 V; TA ≤ 85°C 3
Maximum Quiescent Supply Current ICC 40 μA VIN = VCC or GND; VCC = 5.5 V; TA ≤ 125°C 3
Quiescent Supply Current ICCT 1.35 1.5 1.65 mA VCC = 5.5 V; Input: VIN = 3.4 V; TA = 25°C 3
Output Leakage Current IOFF 0.5 μA VOUT = 5.5 V; VCC = 0.0 V; TA = 25°C 3
Output Leakage Current IOFF 5 μA VOUT = 5.5 V; VCC = 0.0 V; TA ≤ 85°C 3
Output Leakage Current IOFF 10 μA VOUT = 5.5 V; VCC = 0.0 V; TA ≤ 125°C 3
Maximum Input Capacitance CIN 5 10 pF TA = 25°C 3
Maximum Input Capacitance CIN 10 pF TA ≤ 125°C 3
Quiet Output Maximum Dynamic VOL VOLP 0.8 1 V TA = 25°C; Input tr = tf = 3.0 ns, CL = 50 pF, VCC = 5.0 V 3
Quiet Output Minimum Dynamic VOL VOLV -0.8 -1 V TA = 25°C; Input tr = tf = 3.0 ns, CL = 50 pF, VCC = 5.0 V 3
Minimum High Level Dynamic Input Voltage VIHD 2 V TA = 25°C; Input tr = tf = 3.0 ns, CL = 50 pF, VCC = 5.0 V 3
Maximum Low Level Dynamic Input Voltage VILD 0.8 V TA = 25°C; Input tr = tf = 3.0 ns, CL = 50 pF, VCC = 5.0 V 3

CAD (KiCad official)

  • Symbol: MC74VHCT50ADR2G
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOIC-14 (KiCad packages3D, STEP)
  • 3D model files: mc74vhct50adr2g-etched.step / mc74vhct50adr2g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mc74vhct50adr2g.step / mc74vhct50adr2g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (8 pp, sha256 c2f9af5d1b74ee05, retrieved 2026-10-18, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF