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AT25DF081A-SSH-T

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Adesto Technologies NOR FLASH, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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AT25DF081A-SSH-T

Adesto Technologies · NOR FLASH · SOIC-8

AT25DF081A-SSH-T from Adesto Technologies, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CS input Chip select, active low: asserting CS selects the device, and deasserting it deselects the device into standby (not Deep Power-Down) with SO high-impedance and SI ignored.
2 SO (SOI) bidirectional Serial output clocked out on the falling edge of SCK, becoming an input (SOI) during Dual-Input Byte/Page Program, and high-impedance whenever CS is deasserted.
3 WP input Write protect, internally pulled high, controls the hardware locking of protected sectors and is recommended to be externally connected to VCC whenever possible.
4 GND power_in Ground reference for the power supply, which should be connected to the system ground.
5 SI (SIO) bidirectional Serial input latched on the rising edge of SCK, becoming an output (SIO) during Dual-Output Read Array, and ignored whenever the device is deselected.
6 SCK input Serial clock controlling data flow: command, address and input data on SI are latched on the rising edge of SCK, and output data on SO is clocked out on the falling edge.
7 HOLD input Temporarily pauses serial communication while asserted with SO high-impedance, internally pulled high, and requires CS asserted and SCK low to start a Hold condition.
8 VCC power_in Supplies the source voltage to the device within 2.7V to 3.6V; operations at invalid VCC voltages may produce spurious results and should not be attempted.

Key specifications

Parameter Value
Manufacturer Adesto Technologies
Package SOIC-8
Category Memory
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Operating Temperature (Case) Ind. -40 85 °C 43
VCC Power Supply VCC 2.7 3.6 V 43
Temperature under Bias -55 125 °C 43
Storage Temperature -65 150 °C 43
All Input Voltages (including NC Pins) with Respect to Ground -0.6 4.1 V with respect to ground 43
Standby Current ISB 25 50 µA CS, WP, HOLD = VCC, all inputs at CMOS levels 43
Deep Power-down Current IDPD 5 10 µA CS, WP, HOLD = VCC, all inputs at CMOS levels 43
Active Current, Read Operation ICC1 17 20 mA f = 100MHz; IOUT = 0mA; CS = VIL, VCC = Max 43
Active Current, Read Operation ICC1 16 19 mA f = 85MHz; IOUT = 0mA; CS = VIL, VCC = Max 43
Active Current, Read Operation ICC1 15 18 mA f = 66MHz; IOUT = 0mA; CS = VIL, VCC = Max 43
Active Current, Read Operation ICC1 14 17 mA f = 50MHz; IOUT = 0mA; CS = VIL, VCC = Max 43
Active Current, Read Operation ICC1 13 16 mA f = 33MHz; IOUT = 0mA; CS = VIL, VCC = Max 43
Active Current, Read Operation ICC1 12 15 mA f = 20MHz; IOUT = 0mA; CS = VIL, VCC = Max 43
Active Current, Program Operation ICC2 10 15 mA CS = VCC, VCC = Max 43
Active Current, Erase Operation ICC3 12 18 mA CS = VCC, VCC = Max 43
Input Leakage Current ILI 1 µA VIN = CMOS levels 43
Output Leakage Current ILO 1 µA VOUT = CMOS levels 43
Output Low Voltage VOL 0.4 V IOL = 1.6mA; VCC = Min 43
Maximum Clock Frequency for All Operations, RapidS Operation Only fMAX 100 MHz excluding 0Bh, 03h, 3Bh, and 9F opcodes 44
Maximum Clock Frequency for All Operations fCLK 85 MHz excluding 03h and 3Bh opcodes 44
Maximum Clock Frequency for 03h Opcode (Read Array, Low Frequency) fRDLF 50 MHz 03h opcode 44
Maximum Clock Frequency for 3Bh Opcode (Dual-Output Read) fRDDO 85 MHz 3Bh opcode 44
Clock High Time tCLKH 4.3 ns 44
Clock Low Time tCLKL 4.3 ns 44
Clock Rise Time, Peak-to-Peak (Slew Rate) tCLKR 0.1 V/ns 44
Clock Fall Time, Peak-to-Peak (Slew Rate) tCLKF 0.1 V/ns 44
Chip Select High Time tCSH 50 ns 44
Chip Select Low Setup Time (relative to Clock) tCSLS 5 ns 44
Chip Select Low Hold Time (relative to Clock) tCSLH 5 ns 44
Chip Select High Setup Time (relative to Clock) tCSHS 5 ns 44
Chip Select High Hold Time (relative to Clock) tCSHH 5 ns 44
Data In Setup Time tDS 2 ns 44
Data In Hold Time tDH 1 ns 44
Output Disable Time tDIS 5 ns 44
Output Valid Time tV 5 ns 15pF load at frequencies above 70MHz, 30pF otherwise 44
Output Hold Time tOH 2 ns 44
HOLD Low Setup Time (relative to Clock) tHLS 5 ns 44
HOLD Low Hold Time (relative to Clock) tHLH 5 ns 44
HOLD High Setup Time (relative to Clock) tHHS 5 ns 44
HOLD High Hold Time (relative to Clock) tHHH 5 ns 44
HOLD Low to Output High-Z tHLQZ 5 ns 44
HOLD High to Output Low-Z tHHQX 5 ns 44
Write Protect Setup Time tWPS 20 ns 44
Write Protect Hold Time tWPH 100 ns 44
Sector Protect Time (from Chip Select High) tSECP 20 ns from Chip Select High 44
Sector Unprotect Time (from Chip Select High) tSECUP 20 ns from Chip Select High 44
Sector Lockdown and Freeze Sector Lockdown State Time (from Chip Select High) tLOCK 200 µs from Chip Select High 44
Chip Select High to Deep Power-Down tEDPD 1 µs 44
Chip Select High to Standby Mode tRDPD 30 µs 44
Reset Time tRST 30 µs 44
Page Program Time (256-Bytes) tPP 1 3 ms 45
Block Erase Time 4-Kbytes tBLKE 50 200 ms 4-Kbytes 45
Block Erase Time 32-Kbytes tBLKE 250 600 ms 32-Kbytes 45
Block Erase Time 64-Kbytes tBLKE 400 950 ms 64-Kbytes 45
Chip Erase Time tCHPE 16 28 sec 45
OTP Security Register Program Time tOTPP 200 500 µs 45
Write Status Register Time tWRSR 200 ns 45
Minimum VCC to Chip Select Low Time tVCSL 100 µs 45
Power-up Device Delay Before Program or Erase Allowed tPUW 10 ms 45
Power-on Reset Voltage VPOR 1.5 2.5 V 45

CAD (KiCad official)

  • Symbol: AT25DF081A-SSH-T
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: at25df081a-ssh-t-etched.step / at25df081a-ssh-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); at25df081a-ssh-t.step / at25df081a-ssh-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Adesto Technologies datasheet (53 pp, sha256 010d77c4b76447aa, retrieved 2026-10-27, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus off (skipped (clean text read)), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF