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CY8C5287AXI-LP095

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Cypress Semicon Microcontroller Units (MCUs/MPUs/SOCs), TQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentsingle chip microcomputer-microcontrollercy8c5287axi-lp095factory-2.0.0extractor-text

Verified CY8C5287AXI-LP095

by Ray · last 2 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

2 Nov 2026RayPublished by the parts factory: tier mfr, 100 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: CY8C5287AXI-LP095 · TQFP-100(14x14) · 100 pins
  • ✓copper: 100 copper pads, none touching another net
  • ✓datasheet: all 100 pin names found in the 117-page datasheet
  • ✓distributor: lcsc C2959325, digikey CY8C5287AXI-LP095-ND, mouser 727-CY8C5287AXILP095
  • ✓family: TQFP-100_14x14mm_P0.5mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-zhhkdk1h/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 100 pins = 100 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 100 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ cy8c5287axi-lp095.kicad_sym✓ cy8c5287axi-lp095.kicad_mod✓ cy8c5287axi-lp095.step
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3D Model

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Symbol & Footprint

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PCB Footprint

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Datasheet

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Contents

README

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CY8C5287AXI-LP095

Cypress Semicon · Microcontroller Units (MCUs/MPUs/SOCs) · TQFP-100(14x14)

CY8C5287AXI-LP095 from Cypress Semicon, in a TQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P2[5] bidirectional GPIO powered from VDDIO2 with TRACEDATA[1] trace function.
2 P2[6] bidirectional GPIO powered from VDDIO2 with TRACEDATA[2] trace function.
3 P2[7] bidirectional GPIO powered from VDDIO2 with TRACEDATA[3] trace function.
4 P12[4] bidirectional SIO powered from VDDIO2 with I2C0 SCL function (wake from sleep on address match).
5 P12[5] bidirectional SIO powered from VDDIO2 with I2C0 SDA function (wake from sleep on address match).
6 P6[4] bidirectional GPIO powered from VDDIO2.
7 P6[5] bidirectional GPIO powered from VDDIO2.
8 P6[6] bidirectional GPIO powered from VDDIO2.
9 P6[7] bidirectional GPIO powered from VDDIO2.
10 VSSB power_in Ground connection for boost pump.
11 IND passive Inductor connection to boost pump.
12 VBOOST passive Power sense connection to boost pump; boost output available for powering other devices.
13 VBAT power_in Battery supply to boost pump.
14 VSSD power_in Ground for all digital logic and I/O pins; all VSSD pins must be connected together.
15 XRES input External reset pin, active low with internal pull-up.
16 P5[0] bidirectional GPIO powered from VDDIO1.
17 P5[1] bidirectional GPIO powered from VDDIO1.
18 P5[2] bidirectional GPIO powered from VDDIO1.
19 P5[3] bidirectional GPIO powered from VDDIO1.
20 P1[0] bidirectional GPIO with JTAG TMS / SWD SWDIO programming and debug function.
21 P1[1] bidirectional GPIO with JTAG TCK / SWD SWDCK programming and debug function.
22 P1[2] bidirectional GPIO that can be configured as XRES.
23 P1[3] bidirectional GPIO with JTAG TDO and SWV (single wire viewer) output function.
24 P1[4] bidirectional GPIO with JTAG TDI function.
25 P1[5] bidirectional GPIO with optional JTAG nTRST test reset function.
26 VDDIO1 power_in I/O supply for port 1, port 5 and P12[7:6]; 1.71 V to 5.5 V and must be less than or equal to VDDA.
27 P1[6] bidirectional GPIO powered from VDDIO1.
28 P1[7] bidirectional GPIO powered from VDDIO1.
29 P12[6] bidirectional SIO powered from VDDIO1.
30 P12[7] bidirectional SIO powered from VDDIO1.
31 P5[4] bidirectional GPIO powered from VDDIO1.
32 P5[5] bidirectional GPIO powered from VDDIO1.
33 P5[6] bidirectional GPIO powered from VDDIO1.
34 P5[7] bidirectional GPIO powered from VDDIO1.
35 P15[6] bidirectional USBIO D+ connection to USB 2.0 bus (or SWDIO), powered from VDDD; usable as digital I/O.
36 P15[7] bidirectional USBIO D- connection to USB 2.0 bus (or SWDCK), powered from VDDD; usable as digital I/O.
37 VDDD power_in Supply for digital peripherals and digital core regulator; must be at or below VDDA and the two VDDD pins connected together.
38 VSSD power_in Ground for all digital logic and I/O pins; all VSSD pins must be connected together.
39 VCCD passive Digital core regulator output (1.71 V to 1.89 V if externally supplied); the two VCCD pins must be shorted with a 1 uF capacitor to VSSD.
40 NC unconnected No connect.
41 NC unconnected No connect.
42 P15[0] bidirectional GPIO with 4 to 25 MHz crystal oscillator output (XO).
43 P15[1] bidirectional GPIO with 4 to 25 MHz crystal oscillator input (XI).
44 P3[0] bidirectional GPIO powered from VDDIO3 with IDAC1 function.
45 P3[1] bidirectional GPIO powered from VDDIO3 with IDAC3 function.
46 P3[2] bidirectional GPIO powered from VDDIO3 with EXTREF1 external reference input.
47 P3[3] bidirectional GPIO powered from VDDIO3.
48 P3[4] bidirectional GPIO powered from VDDIO3.
49 P3[5] bidirectional GPIO powered from VDDIO3.
50 VDDIO3 power_in I/O supply for port 3, P12[1:0] and P15[3:0]; 1.71 V to 5.5 V and must be less than or equal to VDDA.
51 P3[6] bidirectional GPIO powered from VDDIO3.
52 P3[7] bidirectional GPIO powered from VDDIO3.
53 P12[0] bidirectional SIO powered from VDDIO3 with I2C1 SCL function.
54 P12[1] bidirectional SIO powered from VDDIO3 with I2C1 SDA function.
55 P15[2] bidirectional GPIO with 32.768 kHz crystal oscillator output (XO).
56 P15[3] bidirectional GPIO with 32.768 kHz crystal oscillator input (XI).
57 NC unconnected No connect.
58 NC unconnected No connect.
59 NC unconnected No connect.
60 NC unconnected No connect.
61 NC unconnected No connect.
62 NC unconnected No connect.
63 VCCA power_in Analog core regulator output (1.71 V to 1.89 V if externally supplied); requires 1 uF capacitor to VSSA.
64 VSSA power_in Ground for all analog peripherals.
65 VDDA power_in Supply for analog peripherals and analog core regulator; must be the highest voltage present on the device.
66 VSSD power_in Ground for all digital logic and I/O pins; all VSSD pins must be connected together.
67 P12[2] bidirectional SIO powered from VDDIO0.
68 P12[3] bidirectional SIO powered from VDDIO0.
69 P4[0] bidirectional GPIO powered from VDDIO0.
70 P4[1] bidirectional GPIO powered from VDDIO0.
71 P0[0] bidirectional GPIO powered from VDDIO0.
72 P0[1] bidirectional GPIO powered from VDDIO0.
73 P0[2] bidirectional GPIO powered from VDDIO0 with SAR1 EXTREF external reference.
74 P0[3] bidirectional GPIO powered from VDDIO0 with EXTREF0 external reference input.
75 VDDIO0 power_in I/O supply for port 0, port 4 and P12[3:2]; 1.71 V to 5.5 V and must be less than or equal to VDDA.
76 P0[4] bidirectional GPIO powered from VDDIO0 with SAR0 EXTREF external reference.
77 P0[5] bidirectional GPIO powered from VDDIO0.
78 P0[6] bidirectional GPIO powered from VDDIO0 with IDAC0 low-resistance output.
79 P0[7] bidirectional GPIO powered from VDDIO0 with IDAC2 function.
80 P4[2] bidirectional GPIO powered from VDDIO0.
81 P4[3] bidirectional GPIO powered from VDDIO0.
82 P4[4] bidirectional GPIO powered from VDDIO0.
83 P4[5] bidirectional GPIO powered from VDDIO0.
84 P4[6] bidirectional GPIO powered from VDDIO0.
85 P4[7] bidirectional GPIO powered from VDDIO0.
86 VCCD passive Digital core regulator output (1.71 V to 1.89 V if externally supplied); the two VCCD pins must be shorted with a 1 uF capacitor to VSSD.
87 VSSD power_in Ground for all digital logic and I/O pins; all VSSD pins must be connected together.
88 VDDD power_in Supply for digital peripherals and digital core regulator; must be at or below VDDA and the two VDDD pins connected together.
89 P6[0] bidirectional GPIO powered from VDDIO2.
90 P6[1] bidirectional GPIO powered from VDDIO2.
91 P6[2] bidirectional GPIO powered from VDDIO2.
92 P6[3] bidirectional GPIO powered from VDDIO2.
93 P15[4] bidirectional GPIO powered from VDDIO2.
94 P15[5] bidirectional GPIO powered from VDDIO2.
95 P2[0] bidirectional GPIO powered from VDDIO2.
96 P2[1] bidirectional GPIO powered from VDDIO2.
97 P2[2] bidirectional GPIO powered from VDDIO2.
98 P2[3] bidirectional GPIO powered from VDDIO2 with TRACECLK trace clock function.
99 P2[4] bidirectional GPIO powered from VDDIO2 with TRACEDATA[0] trace function.
100 VDDIO2 power_in I/O supply for port 2, port 6, P12[5:4] and P15[5:4]; 1.71 V to 5.5 V and must be less than or equal to VDDA.

Key specifications

Parameter Value
Manufacturer Cypress Semicon
Package TQFP-100(14x14)
Category Single Chip Microcomputer/Microcontroller
Pins 100

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts gold lead-free products. Lead (Pb) is an alloying element in solders that has resulted in environmental concerns due to potential toxicity. Cypress uses nickel-palladium-gold (NiPdAu) technology for the ma 107

CAD (KiCad official)

  • Symbol: CY8C5287AXI-LP095
  • Footprint: Package_QFP:TQFP-100_14x14mm_P0.5mm
  • 3D model: TQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: cy8c5287axi-lp095-etched.step / cy8c5287axi-lp095-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cy8c5287axi-lp095.step / cy8c5287axi-lp095.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Cypress Semicon datasheet (117 pp, sha256 87963dfadfc60af9, retrieved 2026-11-02, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF