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ACPL-H342-500E
Public Made by Adomby adom
Broadcom AVAGO Logic Output Optoisolators, SOP-8-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownACPL-H342-500E
Broadcom AVAGO · Logic Output Optoisolators · SOP-8-300mil
ACPL-H342-500E from Broadcom AVAGO, in a SOP-8-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 5 | VEE | power_in | Output-side negative supply/ground reference; VCC-VEE must be 15V to 30V recommended (35V absolute max) with a 1 µF bypass capacitor to VCC. |
| 6 | VCLAMP | output | Active Miller clamp output that activates when gate voltage falls below 2.3V relative to VEE, sinking up to 2.5A peak, and should be connected to VEE when not in use. |
| 7 | VOUT | output | Rail-to-rail gate drive output with 2.0A minimum peak high and low output current (2.5A absolute max peak). |
| 8 | VCC | power_in | Positive output supply, 15V to 30V recommended relative to VEE with a 1 µF bypass capacitor between VCC and VEE and UVLO thresholds of 12.3V typ rising and 10.7V typ falling. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Broadcom AVAGO |
| Package | SOP-8-300mil |
| Category | Optoisolators |
| Pins | 4 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating Temperature | TA | -40 | 105 | °C | 7 | ||
| Output Supply Voltage (VCC, VEE) | VCC, VEE | 15 | 30 | V | 7 | ||
| Input Current (ON) | IF(ON) | 7 | 16 | mA | 7 | ||
| Input Voltage (OFF) | VF(OFF) | -3.6 | 0.8 | V | 7 | ||
| Storage Temperature | TS | -55 | 125 | °C | 7 | ||
| Operating Temperature (absolute maximum table) | TA | -40 | 105 | °C | 7 | ||
| Output IC Junction Temperature | TJ | 125 | °C | 7 | |||
| Average Input Current | IF(AVG) | 25 | mA | Derate linearly above 70°C free-air temperature at 0.3 mA/°C | 7 | ||
| Peak Transient Input Current | IF(TRAN) | 1 | A | <1 ms pulse width, 300 pps | 7 | ||
| Reverse Input Voltage | VR | 5 | V | 7 | |||
| High Peak Output Current | IOH(PEAK) | 2.5 | A | Maximum pulse width = 10 μs | 7 | ||
| Low Peak Output Current | IOL(PEAK) | 2.5 | A | Maximum pulse width = 10 μs | 7 | ||
| Peak Clamp Sink Current | ICLAMP | 2.5 | A | Maximum pulse width = 10 μs | 7 | ||
| Total Output Supply Voltage (VCC, VEE) | VCC, VEE | 0 | 35 | V | 7 | ||
| Output Voltage | VO(PEAK) | -0.5 | V | Maximum printed as VCC (not numeric) | 7 | ||
| Output IC Power Dissipation | PO | 500 | mW | Derate linearly above 85°C free-air temperature at 12.5 mW/°C | 7 | ||
| Total Power Dissipation | PT | 550 | mW | Derate linearly above 85°C free-air temperature at 13.75 mW/°C | 7 | ||
| Lead Solder Temperature | 260 | °C | for 10 s, 1.6 mm below seating plane | 7 | |||
| High Level Peak Output Current | IOH | -0.5 | -1.2 | A | VO = VCC, 4V; maximum pulse width 50 μs | 8 | |
| High Level Peak Output Current | IOH | -2 | A | VO = VCC, 15V; maximum pulse width 10 μs | 8 | ||
| Low Level Peak Output Current | IOL | 0.5 | 2.7 | A | VO = VEE + 2.5V; maximum pulse width 50 μs | 8 | |
| Low Level Peak Output Current | IOL | 2 | A | VO = VEE + 15V; maximum pulse width 10 μs | 8 | ||
| High Output Transistor RDS(ON) | RDS,OH | 2.6 | 5 | Ω | IOH = -2.0A | 8 | |
| Low Output Transistor RDS(ON) | RDS,OL | 0.8 | 2 | Ω | IOL = 2.0A | 8 | |
| Clamp Output Peak Current | ICLAMP | 1 | 2.5 | A | VO = VEE + 2.5V; maximum pulse width 10 μs | 8 | |
| Clamp Output Transistor RDS(ON) | RDS,CLAMP | 0.8 | 2 | Ω | ICLAMP = 1.5A | 8 | |
| Low Level Output Voltage | VOL | 0.07 | 0.25 | V | IO = 100 mA | 8 | |
| High Level Supply Current | ICCH | 1.68 | 2.5 | mA | Rg = 10 Ω, Cg = 25 nF, IF = 10 mA | 8 | |
| Low Level Supply Current | ICCL | 2 | 2.5 | mA | Rg = 10 Ω, Cg = 25 nF, IF = 0 mA | 8 | |
| Threshold Input Current Low to High | IFLH | 0.5 | 1.5 | 4 | mA | Rg = 10 Ω, Cg = 25 nF, VO > 5V | 8 |
| Threshold Input Voltage High to Low | VFHL | 0.8 | V | 8 | |||
| Input Forward Voltage | VF | 1.2 | 1.55 | 1.95 | V | IF = 10 mA | 8 |
| Input Reverse Breakdown Voltage | BVR | 5 | V | IR = 100 μA | 8 | ||
| UVLO Threshold (positive going) | VUVLO+ | 11 | 12.3 | 13.5 | V | VO > 5V, IF = 10 mA | 8 |
| UVLO Threshold (negative going) | VUVLO- | 9.5 | 10.7 | 12 | V | VO > 5V, IF = 10 mA | 8 |
| Propagation Delay Time to High Output Level | tPLH | 0.1 | 0.26 | 0.35 | μs | Rg = 10 Ω, Cg = 25 nF, f = 20 kHz, duty cycle = 50%, IF = 7 mA to 16 mA, VCC = 15V to 30V | 9 |
| Propagation Delay Time to Low Output Level | tPHL | 0.05 | 0.145 | 0.25 | μs | 9 | |
| Propagation Delay Difference Between Any Two Parts | PDD (tPHL, tPLH) | -0.01 | -0.1 | -0.2 | μs | 9 | |
| Output High Level Common Mode Transient Immunity | /CMH/ | 40 | 50 | kV/μs | TA = 25 °C, IF = 10 mA, VCC = 30V, VCM = 1500V with split resistors | 9 | |
| Output High Level Common Mode Transient Immunity | /CMH/ | 25 | 35 | kV/μs | TA = 25 °C, IF = 10 mA, VCC = 30V, VCM = 1000V without split resistors | 9 | |
| Output Low Level Common Mode Transient Immunity | /CML/ | 40 | 50 | kV/μs | TA = 25 °C, VF = 0V, VCC = 30V, VCM = 1500V with split resistors | 9 | |
| Output Low Level Common Mode Transient Immunity | /CML/ | 25 | 35 | kV/μs | TA = 25 °C, VF = 0V, VCC = 30V, VCM = 1000V without split resistors | 9 | |
| Input-Output Momentary Withstand Voltage (ACPL-H342) | VISO | 3750 | VRMS | RH < 50%, t = 1 min., TA = 25°C | 10 | ||
| LED-to-Ambient Thermal Resistance | R11 | 145 | °C/W | Thermal model in application notes; high conductivity test board per JEDEC 51-7 | 10 | ||
| LED-to-Detector Thermal Resistance | R12 | 25 | °C/W | Thermal model in application notes; high conductivity test board per JEDEC 51-7 | 10 | ||
| LED-to-Detector Thermal Resistance | R21 | 38 | °C/W | Thermal model in application notes; high conductivity test board per JEDEC 51-7 | 10 | ||
| Detector-to-Ambient Thermal Resistance | R22 | 46 | °C/W | Thermal model in application notes; high conductivity test board per JEDEC 51-7 | 10 |
CAD (KiCad official)
- Symbol:
ACPL-H342-500E - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8-300mil (KiCad packages3D, STEP)
- 3D model files:
acpl-h342-500e-etched.step/acpl-h342-500e-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);acpl-h342-500e.step/acpl-h342-500e.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Broadcom AVAGO datasheet (24 pp, sha256
ce6d2c8260a3ea60, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).