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SN65LVDM050QDQ1

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Texas Instruments LVDS ICs, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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SN65LVDM050QDQ1

Texas Instruments · LVDS ICs · SOIC-16

SN65LVDM050QDQ1 from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1B input Receiver 1 inverting differential input; the receiver detects a differential input of ±50 mV across the A/B pair with up to 1 V of ground potential difference.
2 1A input Receiver 1 non-inverting differential input; the receiver detects a differential input of ±50 mV across the A/B pair with up to 1 V of ground potential difference.
3 1R output Receiver 1 logic output, driven to VOH 2.4 V min at IOH = −8 mA and VOL 0.4 V max at IOL = 8 mA, and high-impedance when RE is high.
4 RE input Receiver enable, active low (receiver output R is high-impedance when RE is high); input VIH 2 V and VIL 0.8 V, LVTTL levels 5 V tolerant.
5 2R output Receiver 2 logic output, driven to VOH 2.4 V min at IOH = −8 mA and VOL 0.4 V max at IOL = 8 mA, and high-impedance when RE is high.
6 2A input Receiver 2 non-inverting differential input; the receiver detects a differential input of ±50 mV across the A/B pair with up to 1 V of ground potential difference.
7 2B input Receiver 2 inverting differential input; the receiver detects a differential input of ±50 mV across the A/B pair with up to 1 V of ground potential difference.
8 GND power_in Device ground; all supply and voltage values are referenced to the network ground terminal.
9 2D input Driver 2 LVTTL data input, 5 V tolerant, which sets the polarity of the 2Y/2Z differential output.
10 2Y output Driver 2 non-inverting LVDS output, typically 340 mV across a 50 Ω load and high-impedance when DE is low or VCC < 1.5 V.
11 2Z output Driver 2 inverting LVDS output, typically 340 mV across a 50 Ω load and high-impedance when DE is low or VCC < 1.5 V.
12 DE input Driver enable, active high (drivers are high-impedance when DE is low); input VIH 2 V and VIL 0.8 V, LVTTL levels 5 V tolerant.
13 1Z output Driver 1 inverting LVDS output, typically 340 mV across a 50 Ω load and high-impedance when DE is low or VCC < 1.5 V.
14 1Y output Driver 1 non-inverting LVDS output, typically 340 mV across a 50 Ω load and high-impedance when DE is low or VCC < 1.5 V.
15 1D input Driver 1 LVTTL data input, 5 V tolerant, which sets the polarity of the 1Y/1Z differential output.
16 VCC power_in Single 3.3 V supply; recommended operating range 3 V to 3.6 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16
Category Interface
Pins 16

CAD (KiCad official)

  • Symbol: SN65LVDM050QDQ1
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: sn65lvdm050qdq1-etched.step / sn65lvdm050qdq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn65lvdm050qdq1.step / sn65lvdm050qdq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (24 pp, sha256 bbb259bd55ba22b0, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF